From 9de30faeac08c368ecc50b74a69bf505096571aa Mon Sep 17 00:00:00 2001 From: Quentin Colombet Date: Wed, 12 Oct 2016 03:57:52 +0000 Subject: [PATCH] [AArch64][InstrustionSelector] Teach the selector about G_BITCAST. llvm-svn: 283973 --- .../Target/AArch64/AArch64InstructionSelector.cpp | 61 +----- .../AArch64/GlobalISel/arm64-instructionselect.mir | 216 ++++++++++++++++++++- 2 files changed, 209 insertions(+), 68 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp index 8c55825..d9d2477 100644 --- a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp @@ -41,32 +41,6 @@ AArch64InstructionSelector::AArch64InstructionSelector( : InstructionSelector(), TM(TM), STI(STI), TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), RBI(RBI) {} -// FIXME: This should be target-independent, inferred from the types declared -// for each class in the bank. -static const TargetRegisterClass * -getRegClassForTypeOnBank(LLT Ty, const RegisterBank &RB, - const RegisterBankInfo &RBI) { - if (RB.getID() == AArch64::GPRRegBankID) { - if (Ty.getSizeInBits() <= 32) - return &AArch64::GPR32RegClass; - if (Ty.getSizeInBits() == 64) - return &AArch64::GPR64RegClass; - return nullptr; - } - - if (RB.getID() == AArch64::FPRRegBankID) { - if (Ty.getSizeInBits() == 32) - return &AArch64::FPR32RegClass; - if (Ty.getSizeInBits() == 64) - return &AArch64::FPR64RegClass; - if (Ty.getSizeInBits() == 128) - return &AArch64::FPR128RegClass; - return nullptr; - } - - return nullptr; -} - /// Check whether \p I is a currently unsupported binary operation: /// - it has an unsized type /// - an operand is not a vreg @@ -579,39 +553,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const { case TargetOpcode::G_INTTOPTR: case TargetOpcode::G_PTRTOINT: - case TargetOpcode::G_BITCAST: { - const LLT DstTy = MRI.getType(I.getOperand(0).getReg()); - const LLT SrcTy = MRI.getType(I.getOperand(1).getReg()); - - const unsigned DstReg = I.getOperand(0).getReg(); - const unsigned SrcReg = I.getOperand(1).getReg(); - - const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); - const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI); - - const TargetRegisterClass *DstRC = - getRegClassForTypeOnBank(DstTy, DstRB, RBI); - if (!DstRC) - return false; - - const TargetRegisterClass *SrcRC = - getRegClassForTypeOnBank(SrcTy, SrcRB, RBI); - if (!SrcRC) - return false; - - if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) || - !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { - DEBUG(dbgs() << "Failed to constrain G_BITCAST\n"); - return false; - } - - BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::COPY)) - .addDef(DstReg) - .addUse(SrcReg); - - I.eraseFromParent(); - return true; - } + case TargetOpcode::G_BITCAST: + return selectCopy(I, TII, MRI, TRI, RBI); } return false; diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir index 1ed869f..fd63ffd 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir @@ -88,6 +88,16 @@ define void @sext_gpr() { ret void } define void @casts() { ret void } + + define void @bitcast_s32_gpr() { ret void } + define void @bitcast_s32_fpr() { ret void } + define void @bitcast_s32_gpr_fpr() { ret void } + define void @bitcast_s32_fpr_gpr() { ret void } + define void @bitcast_s64_gpr() { ret void } + define void @bitcast_s64_fpr() { ret void } + define void @bitcast_s64_gpr_fpr() { ret void } + define void @bitcast_s64_fpr_gpr() { ret void } + ... --- @@ -1436,24 +1446,212 @@ legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64 } -# CHECK-NEXT: - { id: 1, class: fpr64 } +# CHECK-NEXT: - { id: 0, class: gpr64all } +# CHECK-NEXT: - { id: 1, class: gpr64all } +# CHECK-NEXT: - { id: 2, class: gpr64all } +# CHECK-NEXT: - { id: 3, class: gpr64all } registers: - { id: 0, class: gpr } - - { id: 1, class: fpr } + - { id: 1, class: gpr } - { id: 2, class: gpr } - { id: 3, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %0 -# CHECK: %2 = COPY %0 + # CHECK: %2 = COPY %0 # CHECK: %3 = COPY %2 body: | bb.0: - liveins: %w0 + liveins: %x0 %0(s64) = COPY %x0 %1(<8 x s8>) = G_BITCAST %0(s64) %2(p0) = G_INTTOPTR %0 %3(s64) = G_PTRTOINT %2 ... + +--- +# CHECK-LABEL: name: bitcast_s32_gpr +name: bitcast_s32_gpr +legalized: true +regBankSelected: true +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: gpr32all } +# CHECK-NEXT: - { id: 1, class: gpr32all } +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + +# CHECK: body: +# CHECK: %0 = COPY %w0 +# CHECK: %1 = COPY %0 +body: | + bb.0: + liveins: %w0 + + %0(s32) = COPY %w0 + %1(s32) = G_BITCAST %0 +... + +--- +# CHECK-LABEL: name: bitcast_s32_fpr +name: bitcast_s32_fpr +legalized: true +regBankSelected: true + +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: fpr32 } +# CHECK-NEXT: - { id: 1, class: fpr32 } +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + +# CHECK: body: +# CHECK: %0 = COPY %s0 +# CHECK: %1 = COPY %0 +body: | + bb.0: + liveins: %s0 + + %0(s32) = COPY %s0 + %1(s32) = G_BITCAST %0 +... + +--- +# CHECK-LABEL: name: bitcast_s32_gpr_fpr +name: bitcast_s32_gpr_fpr +legalized: true +regBankSelected: true + +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: gpr32all } +# CHECK-NEXT: - { id: 1, class: fpr32 } +registers: + - { id: 0, class: gpr } + - { id: 1, class: fpr } + +# CHECK: body: +# CHECK: %0 = COPY %w0 +# CHECK: %1 = COPY %0 +body: | + bb.0: + liveins: %w0 + + %0(s32) = COPY %w0 + %1(s32) = G_BITCAST %0 +... + +--- +# CHECK-LABEL: name: bitcast_s32_fpr_gpr +name: bitcast_s32_fpr_gpr +legalized: true +regBankSelected: true + +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: fpr32 } +# CHECK-NEXT: - { id: 1, class: gpr32all } +registers: + - { id: 0, class: fpr } + - { id: 1, class: gpr } + +# CHECK: body: +# CHECK: %0 = COPY %s0 +# CHECK: %1 = COPY %0 +body: | + bb.0: + liveins: %s0 + + %0(s32) = COPY %s0 + %1(s32) = G_BITCAST %0 +... + +--- +# CHECK-LABEL: name: bitcast_s64_gpr +name: bitcast_s64_gpr +legalized: true +regBankSelected: true + +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: gpr64all } +# CHECK-NEXT: - { id: 1, class: gpr64all } +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + +# CHECK: body: +# CHECK: %0 = COPY %x0 +# CHECK: %1 = COPY %0 +body: | + bb.0: + liveins: %x0 + + %0(s64) = COPY %x0 + %1(s64) = G_BITCAST %0 +... + +--- +# CHECK-LABEL: name: bitcast_s64_fpr +name: bitcast_s64_fpr +legalized: true +regBankSelected: true + +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: fpr64 } +# CHECK-NEXT: - { id: 1, class: fpr64 } +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + +# CHECK: body: +# CHECK: %0 = COPY %d0 +# CHECK: %1 = COPY %0 +body: | + bb.0: + liveins: %d0 + + %0(s64) = COPY %d0 + %1(s64) = G_BITCAST %0 +... + +--- +# CHECK-LABEL: name: bitcast_s64_gpr_fpr +name: bitcast_s64_gpr_fpr +legalized: true +regBankSelected: true + +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: gpr64all } +# CHECK-NEXT: - { id: 1, class: fpr64 } +registers: + - { id: 0, class: gpr } + - { id: 1, class: fpr } +# CHECK: body: +# CHECK: %0 = COPY %x0 +# CHECK: %1 = COPY %0 +body: | + bb.0: + liveins: %x0 + + %0(s64) = COPY %x0 + %1(s64) = G_BITCAST %0 +... + +--- +# CHECK-LABEL: name: bitcast_s64_fpr_gpr +name: bitcast_s64_fpr_gpr +legalized: true +regBankSelected: true + +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: fpr64 } +# CHECK-NEXT: - { id: 1, class: gpr64all } +registers: + - { id: 0, class: fpr } + - { id: 1, class: gpr } + +# CHECK: body: +# CHECK: %0 = COPY %d0 +# CHECK: %1 = COPY %0 +body: | + bb.0: + liveins: %d0 + + %0(s64) = COPY %d0 + %1(s64) = G_BITCAST %0 +... -- 2.7.4