From 9d07a0bf444c7bafc940ea8f3ba1b1bbbed09793 Mon Sep 17 00:00:00 2001 From: Jingoo Han Date: Tue, 25 Sep 2012 15:48:20 +0900 Subject: [PATCH] video: s3c-fb: move the address definitions for VIDTCON registers The address definitions for VIDTCON registers are moved to right place. Signed-off-by: Jingoo Han --- include/video/samsung_fimd.h | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/include/video/samsung_fimd.h b/include/video/samsung_fimd.h index bd0a04e..bc22f3c 100644 --- a/include/video/samsung_fimd.h +++ b/include/video/samsung_fimd.h @@ -116,6 +116,7 @@ /* VIDTCON0 */ +#define VIDTCON0 (0x10) #define VIDTCON0_VBPDE_MASK (0xff << 24) #define VIDTCON0_VBPDE_SHIFT (24) #define VIDTCON0_VBPDE_LIMIT (0xff) @@ -138,6 +139,7 @@ /* VIDTCON1 */ +#define VIDTCON1 (0x14) #define VIDTCON1_VFPDE_MASK (0xff << 24) #define VIDTCON1_VFPDE_SHIFT (24) #define VIDTCON1_VFPDE_LIMIT (0xff) @@ -159,6 +161,7 @@ #define VIDTCON1_HSPW(_x) ((_x) << 0) #define VIDTCON2 (0x18) +#define VIDTCON2 (0x18) #define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23) #define VIDTCON2_LINEVAL_MASK (0x7ff << 11) #define VIDTCON2_LINEVAL_SHIFT (11) @@ -405,11 +408,6 @@ #define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */ #define VIDCON1_FSTATUS_EVEN (1 << 15) -/* Video timing controls */ -#define VIDTCON0 (0x10) -#define VIDTCON1 (0x14) -#define VIDTCON2 (0x18) - /* OSD1 and OSD4 do not have register D */ #define VIDOSD_BASE (0x40) -- 2.7.4