From 9ceef3d9a7f02f2780986fa97391163c720ddf3f Mon Sep 17 00:00:00 2001 From: Eugen Hristev Date: Mon, 15 May 2023 12:59:45 +0300 Subject: [PATCH] ARM: dts: rockchip: rk3588-rock-5b-u-boot: add USB 2.0 host Add USB 2.0 host nodes and PHYs. Reviewed-by: Kever Yang Co-developed-by: William Wu Signed-off-by: William Wu Signed-off-by: Eugen Hristev --- arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 82 +++++++++++++++++++++++++++++++ arch/arm/dts/rk3588s-u-boot.dtsi | 86 +++++++++++++++++++++++++++++++++ 2 files changed, 168 insertions(+) diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi index 85075bf..53d029c 100644 --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi @@ -4,6 +4,9 @@ */ #include "rk3588-u-boot.dtsi" +#include +#include +#include / { aliases { @@ -13,6 +16,26 @@ chosen { u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci; }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&pinctrl { + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; &sdmmc { @@ -27,3 +50,62 @@ pinctrl-names = "default"; pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_data_strobe &emmc_rstnout>; }; + +&usb_host0_ehci { + companion = <&usb_host0_ohci>; + phys = <&u2phy2_host>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +&usb_host0_ohci { + phys = <&u2phy2_host>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +&usb2phy2_grf { + status = "okay"; +}; + +&u2phy2 { + resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; + reset-names = "phy", "apb"; + clock-output-names = "usb480m_phy2"; + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb_host1_ehci { + companion = <&usb_host1_ohci>; + phys = <&u2phy3_host>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +&usb_host1_ohci { + phys = <&u2phy3_host>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +&usb2phy3_grf { + status = "okay"; +}; + +&u2phy3 { + resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; + reset-names = "phy", "apb"; + clock-output-names = "usb480m_phy3"; + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi index 5201ba2..cd7e6cb 100644 --- a/arch/arm/dts/rk3588s-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-u-boot.dtsi @@ -12,12 +12,98 @@ status = "okay"; }; + usb_host0_ehci: usb@fc800000 { + compatible = "generic-ehci"; + reg = <0x0 0xfc800000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>; + clock-names = "usbhost", "arbiter"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + + usb_host0_ohci: usb@fc840000 { + compatible = "generic-ohci"; + reg = <0x0 0xfc840000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>; + clock-names = "usbhost", "arbiter"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + + usb_host1_ehci: usb@fc880000 { + compatible = "generic-ehci"; + reg = <0x0 0xfc880000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>; + clock-names = "usbhost", "arbiter"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + + usb_host1_ohci: usb@fc8c0000 { + compatible = "generic-ohci"; + reg = <0x0 0xfc8c0000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>; + clock-names = "usbhost", "arbiter"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + pmu1_grf: syscon@fd58a000 { bootph-all; compatible = "rockchip,rk3588-pmu1-grf", "syscon"; reg = <0x0 0xfd58a000 0x0 0x2000>; }; + usb2phy2_grf: syscon@fd5d8000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", + "simple-mfd"; + reg = <0x0 0xfd5d8000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy2: usb2-phy@8000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x8000 0x10>; + interrupts = ; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + #clock-cells = <0>; + status = "disabled"; + + u2phy2_host: host-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + usb2phy3_grf: syscon@fd5dc000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", + "simple-mfd"; + reg = <0x0 0xfd5dc000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy3: usb2-phy@c000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0xc000 0x10>; + interrupts = ; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + #clock-cells = <0>; + status = "disabled"; + + u2phy3_host: host-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + otp: nvmem@fecc0000 { compatible = "rockchip,rk3588-otp"; reg = <0x0 0xfecc0000 0x0 0x400>; -- 2.7.4