From 9c64caeb261ffcba36d2bae0e381da3b3d65d95a Mon Sep 17 00:00:00 2001 From: Joonyoung Shim Date: Wed, 1 Oct 2014 21:27:35 +0900 Subject: [PATCH] odroid: fix g2d sclk rate G2D core should be provided 200MHz clock rate. Change-Id: If06eb7d4433d302767f04e7c8b487cdcd32321a4 Signed-off-by: Joonyoung Shim --- board/samsung/common/exynos4-dt.c | 4 ++-- board/samsung/odroid/odroid.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/board/samsung/common/exynos4-dt.c b/board/samsung/common/exynos4-dt.c index 92cef40c85..cefc4d7267 100644 --- a/board/samsung/common/exynos4-dt.c +++ b/board/samsung/common/exynos4-dt.c @@ -408,12 +408,12 @@ static void board_clock_init(void) * MOUTc2c = 800 Mhz * MOUTpwi = 108 MHz * - * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 400 (1) + * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 200 (3) * sclk_c2c = MOUTc2c / (ratio + 1) = 400 (1) * aclk_c2c = sclk_c2c / (ratio + 1) = 200 (1) * sclk_pwi = MOUTpwi / (ratio + 1) = 18 (5) */ - set = G2D_ACP_RATIO(1) | C2C_RATIO(1) | PWI_RATIO(5) | + set = G2D_ACP_RATIO(3) | C2C_RATIO(1) | PWI_RATIO(5) | C2C_ACLK_RATIO(1) | DVSEM_RATIO(1) | DPM_RATIO(1); clrsetbits_le32(&clk->div_dmc1, clr, set); diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c index ac19527a90..d380442cda 100644 --- a/board/samsung/odroid/odroid.c +++ b/board/samsung/odroid/odroid.c @@ -248,12 +248,12 @@ static void board_clock_init(void) * MOUTc2c = 800 Mhz * MOUTpwi = 108 MHz * - * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 400 (1) + * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 200 (3) * sclk_c2c = MOUTc2c / (ratio + 1) = 400 (1) * aclk_c2c = sclk_c2c / (ratio + 1) = 200 (1) * sclk_pwi = MOUTpwi / (ratio + 1) = 18 (5) */ - set = G2D_ACP_RATIO(1) | C2C_RATIO(1) | PWI_RATIO(5) | + set = G2D_ACP_RATIO(3) | C2C_RATIO(1) | PWI_RATIO(5) | C2C_ACLK_RATIO(1) | DVSEM_RATIO(1) | DPM_RATIO(1); clrsetbits_le32(&clk->div_dmc1, clr, set); -- 2.34.1