From 9c144dc81e11658c868867052d14d60cca55a641 Mon Sep 17 00:00:00 2001 From: Anuj Phogat Date: Tue, 6 Feb 2018 16:47:04 -0800 Subject: [PATCH] i965/icl: Add assertions to check dispatch mode is SIMD8 SIMD4x2 dispatch mode has been removed in GEN11. We're not using it anyways in Mesa. Adding few asserts to make it explicit. Use GEN_GEN macro in place of devinfo->gen (Ken) Signed-off-by: Anuj Phogat Reviewed-by: Kenneth Graunke --- src/intel/blorp/blorp_genX_exec.h | 2 ++ src/mesa/drivers/dri/i965/genX_state_upload.c | 5 +++++ 2 files changed, 7 insertions(+) diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h index 0fcb94f..737720a 100644 --- a/src/intel/blorp/blorp_genX_exec.h +++ b/src/intel/blorp/blorp_genX_exec.h @@ -572,6 +572,8 @@ blorp_emit_vs_config(struct blorp_batch *batch, const struct blorp_params *params) { struct brw_vs_prog_data *vs_prog_data = params->vs_prog_data; + assert(!vs_prog_data || GEN_GEN < 11 || + vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8); blorp_emit(batch, GENX(3DSTATE_VS), vs) { if (vs_prog_data) { diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c b/src/mesa/drivers/dri/i965/genX_state_upload.c index b171c4f..8668abd 100644 --- a/src/mesa/drivers/dri/i965/genX_state_upload.c +++ b/src/mesa/drivers/dri/i965/genX_state_upload.c @@ -2050,6 +2050,8 @@ genX(upload_vs_state)(struct brw_context *brw) assert(vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8 || vue_prog_data->dispatch_mode == DISPATCH_MODE_4X2_DUAL_OBJECT); + assert(GEN_GEN < 11 || + vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8); #if GEN_GEN == 6 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State, @@ -3967,6 +3969,9 @@ genX(upload_ds_state)(struct brw_context *brw) if (!tes_prog_data) { brw_batch_emit(brw, GENX(3DSTATE_DS), ds); } else { + assert(GEN_GEN < 11 || + vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8); + brw_batch_emit(brw, GENX(3DSTATE_DS), ds) { INIT_THREAD_DISPATCH_FIELDS(ds, Patch); -- 2.7.4