From 9c0551f23e653e848681d651603e3122e18a1c65 Mon Sep 17 00:00:00 2001 From: Jiansong Chen Date: Tue, 21 Jul 2020 12:21:40 +0800 Subject: [PATCH] drm/amd/powerplay: fix typos for clk map It should be DCLK1->PPCLK_DCLK_1 and VCLK->PPCLK_VCLK_0. Signed-off-by: Jiansong Chen Reviewed-by: Likun Gao Acked-by: Tao Zhou Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c index cae8e77..87eedd7 100644 --- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c @@ -128,8 +128,8 @@ static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = { CLK_MAP(UCLK, PPCLK_UCLK), CLK_MAP(MCLK, PPCLK_UCLK), CLK_MAP(DCLK, PPCLK_DCLK_0), - CLK_MAP(DCLK1, PPCLK_DCLK_0), - CLK_MAP(VCLK, PPCLK_VCLK_1), + CLK_MAP(DCLK1, PPCLK_DCLK_1), + CLK_MAP(VCLK, PPCLK_VCLK_0), CLK_MAP(VCLK1, PPCLK_VCLK_1), CLK_MAP(DCEFCLK, PPCLK_DCEFCLK), CLK_MAP(DISPCLK, PPCLK_DISPCLK), -- 2.7.4