From 9bd7b149c2f577086a716ccd0363d057caa3d98a Mon Sep 17 00:00:00 2001 From: David Green Date: Thu, 13 Apr 2023 11:57:32 +0100 Subject: [PATCH] [ARM] Replace some uses of -mcpu=cortex-m33 with architectures features. NFC This adjusts some of the tests to use the architecture features directly as opposed to -mcpu=cortex-m33 names. --- llvm/test/CodeGen/ARM/ParallelDSP/aliasing.ll | 2 +- .../CodeGen/ARM/ParallelDSP/multi-use-loads.ll | 186 +++++++++------------ llvm/test/CodeGen/ARM/ParallelDSP/smlad0.ll | 8 +- llvm/test/CodeGen/ARM/ParallelDSP/smlad1.ll | 2 +- llvm/test/CodeGen/ARM/ParallelDSP/smlad10.ll | 2 +- llvm/test/CodeGen/ARM/ParallelDSP/smlad11.ll | 2 +- llvm/test/CodeGen/ARM/ParallelDSP/smlad12.ll | 2 +- llvm/test/CodeGen/ARM/ParallelDSP/smlad2.ll | 2 +- llvm/test/CodeGen/ARM/ParallelDSP/smlad3.ll | 2 +- llvm/test/CodeGen/ARM/ParallelDSP/smlad4.ll | 2 +- llvm/test/CodeGen/ARM/ParallelDSP/smlad5.ll | 2 +- llvm/test/CodeGen/ARM/ParallelDSP/smlad8.ll | 2 +- llvm/test/CodeGen/ARM/ParallelDSP/smlad9.ll | 2 +- llvm/test/CodeGen/ARM/ParallelDSP/smladx-1.ll | 8 +- llvm/test/CodeGen/ARM/ParallelDSP/smlald0.ll | 8 +- llvm/test/CodeGen/ARM/ParallelDSP/smlald1.ll | 2 +- llvm/test/CodeGen/ARM/ParallelDSP/smlald2.ll | 6 +- llvm/test/CodeGen/ARM/ParallelDSP/smlaldx-1.ll | 6 +- llvm/test/CodeGen/ARM/ParallelDSP/smlaldx-2.ll | 6 +- 19 files changed, 116 insertions(+), 136 deletions(-) diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/aliasing.ll b/llvm/test/CodeGen/ARM/ParallelDSP/aliasing.ll index b75f7af..9526969 100644 --- a/llvm/test/CodeGen/ARM/ParallelDSP/aliasing.ll +++ b/llvm/test/CodeGen/ARM/ParallelDSP/aliasing.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -mtriple=arm-none-none-eabi -mcpu=cortex-m33 < %s -arm-parallel-dsp -verify -S | FileCheck %s +; RUN: opt -mtriple=armv8m.main-none-none-eabi -mattr=+dsp < %s -arm-parallel-dsp -verify -S | FileCheck %s ; ; Alias check: check that the rewrite isn't triggered when there's a store ; instruction possibly aliasing any mul load operands; arguments are passed diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/multi-use-loads.ll b/llvm/test/CodeGen/ARM/ParallelDSP/multi-use-loads.ll index 3d60686..050696a 100644 --- a/llvm/test/CodeGen/ARM/ParallelDSP/multi-use-loads.ll +++ b/llvm/test/CodeGen/ARM/ParallelDSP/multi-use-loads.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -O3 -mtriple=arm-none-none-eabi -mcpu=cortex-m33 < %s | FileCheck %s --check-prefixes=CHECK-LE -; RUN: llc -O3 -mtriple=armeb-none-none-eabi -mcpu=cortex-m33 < %s | FileCheck %s --check-prefixes=CHECK-BE +; RUN: llc -O3 -mtriple=armv8m.main-none-none-eabi -mattr=+dsp < %s | FileCheck %s --check-prefixes=CHECK-LE +; RUN: llc -O3 -mtriple=armv8m.maineb-none-none-eabi -mattr=+dsp < %s | FileCheck %s --check-prefixes=CHECK-BE define i32 @add_user(i32 %arg, ptr nocapture readnone %arg1, ptr nocapture readonly %arg2, ptr nocapture readonly %arg3) { ; CHECK-LE-LABEL: add_user: @@ -10,23 +10,21 @@ define i32 @add_user(i32 %arg, ptr nocapture readnone %arg1, ptr nocapture reado ; CHECK-LE-NEXT: cmp r0, #1 ; CHECK-LE-NEXT: blt .LBB0_4 ; CHECK-LE-NEXT: @ %bb.1: @ %for.body.preheader +; CHECK-LE-NEXT: sub.w lr, r3, #2 ; CHECK-LE-NEXT: subs r2, #2 -; CHECK-LE-NEXT: subs r3, #2 ; CHECK-LE-NEXT: mov.w r12, #0 ; CHECK-LE-NEXT: movs r1, #0 -; CHECK-LE-NEXT: .p2align 2 ; CHECK-LE-NEXT: .LBB0_2: @ %for.body ; CHECK-LE-NEXT: @ =>This Inner Loop Header: Depth=1 -; CHECK-LE-NEXT: ldr lr, [r3, #2]! -; CHECK-LE-NEXT: ldr r4, [r2, #2]! +; CHECK-LE-NEXT: ldr r3, [lr, #2]! ; CHECK-LE-NEXT: subs r0, #1 -; CHECK-LE-NEXT: smlad r12, r4, lr, r12 -; CHECK-LE-NEXT: sxtah r1, r1, lr +; CHECK-LE-NEXT: ldr r4, [r2, #2]! +; CHECK-LE-NEXT: sxtah r1, r1, r3 +; CHECK-LE-NEXT: smlad r12, r4, r3, r12 ; CHECK-LE-NEXT: bne .LBB0_2 ; CHECK-LE-NEXT: @ %bb.3: @ %for.cond.cleanup ; CHECK-LE-NEXT: add.w r0, r12, r1 ; CHECK-LE-NEXT: pop {r4, pc} -; CHECK-LE-NEXT: .p2align 2 ; CHECK-LE-NEXT: .LBB0_4: ; CHECK-LE-NEXT: mov.w r12, #0 ; CHECK-LE-NEXT: movs r1, #0 @@ -35,36 +33,34 @@ define i32 @add_user(i32 %arg, ptr nocapture readnone %arg1, ptr nocapture reado ; ; CHECK-BE-LABEL: add_user: ; CHECK-BE: @ %bb.0: @ %entry -; CHECK-BE-NEXT: .save {r4, r5, r6, lr} -; CHECK-BE-NEXT: push {r4, r5, r6, lr} +; CHECK-BE-NEXT: .save {r4, r5, r7, lr} +; CHECK-BE-NEXT: push {r4, r5, r7, lr} ; CHECK-BE-NEXT: cmp r0, #1 ; CHECK-BE-NEXT: blt .LBB0_4 ; CHECK-BE-NEXT: @ %bb.1: @ %for.body.preheader -; CHECK-BE-NEXT: subs r2, #2 ; CHECK-BE-NEXT: subs r3, #2 +; CHECK-BE-NEXT: subs r2, #2 ; CHECK-BE-NEXT: mov.w r12, #0 ; CHECK-BE-NEXT: movs r1, #0 -; CHECK-BE-NEXT: .p2align 2 ; CHECK-BE-NEXT: .LBB0_2: @ %for.body ; CHECK-BE-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-BE-NEXT: ldrsh lr, [r3, #2]! -; CHECK-BE-NEXT: ldrsh r5, [r2, #2]! -; CHECK-BE-NEXT: ldrsh.w r4, [r3, #2] -; CHECK-BE-NEXT: ldrsh.w r6, [r2, #2] -; CHECK-BE-NEXT: smlabb r5, r5, lr, r12 -; CHECK-BE-NEXT: add r1, lr ; CHECK-BE-NEXT: subs r0, #1 -; CHECK-BE-NEXT: smlabb r12, r6, r4, r5 +; CHECK-BE-NEXT: ldrsh r4, [r2, #2]! +; CHECK-BE-NEXT: add r1, lr +; CHECK-BE-NEXT: ldrsh.w r5, [r2, #2] +; CHECK-BE-NEXT: smlabb r12, r4, lr, r12 +; CHECK-BE-NEXT: ldrsh.w r4, [r3, #2] +; CHECK-BE-NEXT: smlabb r12, r5, r4, r12 ; CHECK-BE-NEXT: bne .LBB0_2 ; CHECK-BE-NEXT: @ %bb.3: @ %for.cond.cleanup ; CHECK-BE-NEXT: add.w r0, r12, r1 -; CHECK-BE-NEXT: pop {r4, r5, r6, pc} -; CHECK-BE-NEXT: .p2align 2 +; CHECK-BE-NEXT: pop {r4, r5, r7, pc} ; CHECK-BE-NEXT: .LBB0_4: ; CHECK-BE-NEXT: mov.w r12, #0 ; CHECK-BE-NEXT: movs r1, #0 ; CHECK-BE-NEXT: add.w r0, r12, r1 -; CHECK-BE-NEXT: pop {r4, r5, r6, pc} +; CHECK-BE-NEXT: pop {r4, r5, r7, pc} entry: %cmp24 = icmp sgt i32 %arg, 0 br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup @@ -109,67 +105,63 @@ for.body: define i32 @mul_bottom_user(i32 %arg, ptr nocapture readnone %arg1, ptr nocapture readonly %arg2, ptr nocapture readonly %arg3) { ; CHECK-LE-LABEL: mul_bottom_user: ; CHECK-LE: @ %bb.0: @ %entry -; CHECK-LE-NEXT: .save {r4, r5, r7, lr} -; CHECK-LE-NEXT: push {r4, r5, r7, lr} +; CHECK-LE-NEXT: .save {r4, lr} +; CHECK-LE-NEXT: push {r4, lr} ; CHECK-LE-NEXT: cmp r0, #1 ; CHECK-LE-NEXT: blt .LBB1_4 ; CHECK-LE-NEXT: @ %bb.1: @ %for.body.preheader -; CHECK-LE-NEXT: sub.w lr, r2, #2 -; CHECK-LE-NEXT: subs r3, #2 +; CHECK-LE-NEXT: sub.w lr, r3, #2 +; CHECK-LE-NEXT: subs r2, #2 ; CHECK-LE-NEXT: mov.w r12, #0 ; CHECK-LE-NEXT: movs r1, #0 -; CHECK-LE-NEXT: .p2align 2 ; CHECK-LE-NEXT: .LBB1_2: @ %for.body ; CHECK-LE-NEXT: @ =>This Inner Loop Header: Depth=1 -; CHECK-LE-NEXT: ldr r2, [r3, #2]! -; CHECK-LE-NEXT: ldr r4, [lr, #2]! -; CHECK-LE-NEXT: sxth r5, r2 -; CHECK-LE-NEXT: smlad r12, r4, r2, r12 +; CHECK-LE-NEXT: ldr r3, [lr, #2]! ; CHECK-LE-NEXT: subs r0, #1 -; CHECK-LE-NEXT: mul r1, r5, r1 +; CHECK-LE-NEXT: ldr r4, [r2, #2]! +; CHECK-LE-NEXT: smlad r12, r4, r3, r12 +; CHECK-LE-NEXT: sxth r3, r3 +; CHECK-LE-NEXT: mul r1, r3, r1 ; CHECK-LE-NEXT: bne .LBB1_2 ; CHECK-LE-NEXT: @ %bb.3: @ %for.cond.cleanup ; CHECK-LE-NEXT: add.w r0, r12, r1 -; CHECK-LE-NEXT: pop {r4, r5, r7, pc} -; CHECK-LE-NEXT: .p2align 2 +; CHECK-LE-NEXT: pop {r4, pc} ; CHECK-LE-NEXT: .LBB1_4: ; CHECK-LE-NEXT: mov.w r12, #0 ; CHECK-LE-NEXT: movs r1, #0 ; CHECK-LE-NEXT: add.w r0, r12, r1 -; CHECK-LE-NEXT: pop {r4, r5, r7, pc} +; CHECK-LE-NEXT: pop {r4, pc} ; ; CHECK-BE-LABEL: mul_bottom_user: ; CHECK-BE: @ %bb.0: @ %entry -; CHECK-BE-NEXT: .save {r4, r5, r6, lr} -; CHECK-BE-NEXT: push {r4, r5, r6, lr} +; CHECK-BE-NEXT: .save {r4, r5, r7, lr} +; CHECK-BE-NEXT: push {r4, r5, r7, lr} ; CHECK-BE-NEXT: cmp r0, #1 ; CHECK-BE-NEXT: blt .LBB1_4 ; CHECK-BE-NEXT: @ %bb.1: @ %for.body.preheader -; CHECK-BE-NEXT: subs r2, #2 ; CHECK-BE-NEXT: subs r3, #2 +; CHECK-BE-NEXT: subs r2, #2 ; CHECK-BE-NEXT: mov.w r12, #0 ; CHECK-BE-NEXT: movs r1, #0 -; CHECK-BE-NEXT: .p2align 2 ; CHECK-BE-NEXT: .LBB1_2: @ %for.body ; CHECK-BE-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-BE-NEXT: ldrsh lr, [r3, #2]! -; CHECK-BE-NEXT: ldrsh r4, [r2, #2]! -; CHECK-BE-NEXT: ldrsh.w r5, [r3, #2] -; CHECK-BE-NEXT: ldrsh.w r6, [r2, #2] -; CHECK-BE-NEXT: smlabb r4, r4, lr, r12 -; CHECK-BE-NEXT: smlabb r12, r6, r5, r4 ; CHECK-BE-NEXT: subs r0, #1 +; CHECK-BE-NEXT: ldrsh r4, [r2, #2]! +; CHECK-BE-NEXT: ldrsh.w r5, [r2, #2] ; CHECK-BE-NEXT: mul r1, lr, r1 +; CHECK-BE-NEXT: smlabb r12, r4, lr, r12 +; CHECK-BE-NEXT: ldrsh.w r4, [r3, #2] +; CHECK-BE-NEXT: smlabb r12, r5, r4, r12 ; CHECK-BE-NEXT: bne .LBB1_2 ; CHECK-BE-NEXT: @ %bb.3: @ %for.cond.cleanup ; CHECK-BE-NEXT: add.w r0, r12, r1 -; CHECK-BE-NEXT: pop {r4, r5, r6, pc} -; CHECK-BE-NEXT: .p2align 2 +; CHECK-BE-NEXT: pop {r4, r5, r7, pc} ; CHECK-BE-NEXT: .LBB1_4: ; CHECK-BE-NEXT: mov.w r12, #0 ; CHECK-BE-NEXT: movs r1, #0 ; CHECK-BE-NEXT: add.w r0, r12, r1 -; CHECK-BE-NEXT: pop {r4, r5, r6, pc} +; CHECK-BE-NEXT: pop {r4, r5, r7, pc} entry: %cmp24 = icmp sgt i32 %arg, 0 br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup @@ -219,16 +211,15 @@ define i32 @mul_top_user(i32 %arg, ptr nocapture readnone %arg1, ptr nocapture r ; CHECK-LE-NEXT: cmp r0, #1 ; CHECK-LE-NEXT: blt .LBB2_4 ; CHECK-LE-NEXT: @ %bb.1: @ %for.body.preheader -; CHECK-LE-NEXT: subs r2, #2 ; CHECK-LE-NEXT: subs r3, #2 +; CHECK-LE-NEXT: subs r2, #2 ; CHECK-LE-NEXT: mov.w r12, #0 ; CHECK-LE-NEXT: movs r1, #0 -; CHECK-LE-NEXT: .p2align 2 ; CHECK-LE-NEXT: .LBB2_2: @ %for.body ; CHECK-LE-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-LE-NEXT: ldr lr, [r3, #2]! -; CHECK-LE-NEXT: ldr r4, [r2, #2]! ; CHECK-LE-NEXT: subs r0, #1 +; CHECK-LE-NEXT: ldr r4, [r2, #2]! ; CHECK-LE-NEXT: smlad r12, r4, lr, r12 ; CHECK-LE-NEXT: asr.w r4, r4, #16 ; CHECK-LE-NEXT: mul r1, r4, r1 @@ -236,7 +227,6 @@ define i32 @mul_top_user(i32 %arg, ptr nocapture readnone %arg1, ptr nocapture r ; CHECK-LE-NEXT: @ %bb.3: @ %for.cond.cleanup ; CHECK-LE-NEXT: add.w r0, r12, r1 ; CHECK-LE-NEXT: pop {r4, pc} -; CHECK-LE-NEXT: .p2align 2 ; CHECK-LE-NEXT: .LBB2_4: ; CHECK-LE-NEXT: mov.w r12, #0 ; CHECK-LE-NEXT: movs r1, #0 @@ -245,36 +235,34 @@ define i32 @mul_top_user(i32 %arg, ptr nocapture readnone %arg1, ptr nocapture r ; ; CHECK-BE-LABEL: mul_top_user: ; CHECK-BE: @ %bb.0: @ %entry -; CHECK-BE-NEXT: .save {r4, r5, r6, lr} -; CHECK-BE-NEXT: push {r4, r5, r6, lr} +; CHECK-BE-NEXT: .save {r4, lr} +; CHECK-BE-NEXT: push {r4, lr} ; CHECK-BE-NEXT: cmp r0, #1 ; CHECK-BE-NEXT: blt .LBB2_4 ; CHECK-BE-NEXT: @ %bb.1: @ %for.body.preheader -; CHECK-BE-NEXT: subs r2, #2 ; CHECK-BE-NEXT: subs r3, #2 +; CHECK-BE-NEXT: subs r2, #2 ; CHECK-BE-NEXT: mov.w r12, #0 ; CHECK-BE-NEXT: movs r1, #0 -; CHECK-BE-NEXT: .p2align 2 ; CHECK-BE-NEXT: .LBB2_2: @ %for.body ; CHECK-BE-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-BE-NEXT: ldrsh lr, [r3, #2]! -; CHECK-BE-NEXT: ldrsh r4, [r2, #2]! -; CHECK-BE-NEXT: ldrsh.w r5, [r3, #2] -; CHECK-BE-NEXT: ldrsh.w r6, [r2, #2] -; CHECK-BE-NEXT: smlabb r4, r4, lr, r12 -; CHECK-BE-NEXT: smlabb r12, r6, r5, r4 ; CHECK-BE-NEXT: subs r0, #1 -; CHECK-BE-NEXT: mul r1, r6, r1 +; CHECK-BE-NEXT: ldrsh r4, [r2, #2]! +; CHECK-BE-NEXT: smlabb r12, r4, lr, r12 +; CHECK-BE-NEXT: ldrsh.w r4, [r2, #2] +; CHECK-BE-NEXT: ldrsh.w lr, [r3, #2] +; CHECK-BE-NEXT: mul r1, r4, r1 +; CHECK-BE-NEXT: smlabb r12, r4, lr, r12 ; CHECK-BE-NEXT: bne .LBB2_2 ; CHECK-BE-NEXT: @ %bb.3: @ %for.cond.cleanup ; CHECK-BE-NEXT: add.w r0, r12, r1 -; CHECK-BE-NEXT: pop {r4, r5, r6, pc} -; CHECK-BE-NEXT: .p2align 2 +; CHECK-BE-NEXT: pop {r4, pc} ; CHECK-BE-NEXT: .LBB2_4: ; CHECK-BE-NEXT: mov.w r12, #0 ; CHECK-BE-NEXT: movs r1, #0 ; CHECK-BE-NEXT: add.w r0, r12, r1 -; CHECK-BE-NEXT: pop {r4, r5, r6, pc} +; CHECK-BE-NEXT: pop {r4, pc} entry: %cmp24 = icmp sgt i32 %arg, 0 br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup @@ -324,24 +312,22 @@ define i32 @and_user(i32 %arg, ptr nocapture readnone %arg1, ptr nocapture reado ; CHECK-LE-NEXT: cmp r0, #1 ; CHECK-LE-NEXT: blt .LBB3_4 ; CHECK-LE-NEXT: @ %bb.1: @ %for.body.preheader -; CHECK-LE-NEXT: sub.w lr, r2, #2 -; CHECK-LE-NEXT: subs r3, #2 +; CHECK-LE-NEXT: sub.w lr, r3, #2 +; CHECK-LE-NEXT: subs r2, #2 ; CHECK-LE-NEXT: mov.w r12, #0 ; CHECK-LE-NEXT: movs r1, #0 -; CHECK-LE-NEXT: .p2align 2 ; CHECK-LE-NEXT: .LBB3_2: @ %for.body ; CHECK-LE-NEXT: @ =>This Inner Loop Header: Depth=1 -; CHECK-LE-NEXT: ldr r2, [r3, #2]! -; CHECK-LE-NEXT: ldr r4, [lr, #2]! +; CHECK-LE-NEXT: ldr r3, [lr, #2]! ; CHECK-LE-NEXT: subs r0, #1 -; CHECK-LE-NEXT: smlad r12, r4, r2, r12 -; CHECK-LE-NEXT: uxth r2, r2 -; CHECK-LE-NEXT: mul r1, r2, r1 +; CHECK-LE-NEXT: ldr r4, [r2, #2]! +; CHECK-LE-NEXT: smlad r12, r4, r3, r12 +; CHECK-LE-NEXT: uxth r3, r3 +; CHECK-LE-NEXT: mul r1, r3, r1 ; CHECK-LE-NEXT: bne .LBB3_2 ; CHECK-LE-NEXT: @ %bb.3: @ %for.cond.cleanup ; CHECK-LE-NEXT: add.w r0, r12, r1 ; CHECK-LE-NEXT: pop {r4, pc} -; CHECK-LE-NEXT: .p2align 2 ; CHECK-LE-NEXT: .LBB3_4: ; CHECK-LE-NEXT: mov.w r12, #0 ; CHECK-LE-NEXT: movs r1, #0 @@ -350,36 +336,34 @@ define i32 @and_user(i32 %arg, ptr nocapture readnone %arg1, ptr nocapture reado ; ; CHECK-BE-LABEL: and_user: ; CHECK-BE: @ %bb.0: @ %entry -; CHECK-BE-NEXT: .save {r4, r5, r6, lr} -; CHECK-BE-NEXT: push {r4, r5, r6, lr} +; CHECK-BE-NEXT: .save {r4, r5, r7, lr} +; CHECK-BE-NEXT: push {r4, r5, r7, lr} ; CHECK-BE-NEXT: cmp r0, #1 ; CHECK-BE-NEXT: blt .LBB3_4 ; CHECK-BE-NEXT: @ %bb.1: @ %for.body.preheader -; CHECK-BE-NEXT: subs r2, #2 ; CHECK-BE-NEXT: subs r3, #2 +; CHECK-BE-NEXT: subs r2, #2 ; CHECK-BE-NEXT: mov.w r12, #0 ; CHECK-BE-NEXT: movs r1, #0 -; CHECK-BE-NEXT: .p2align 2 ; CHECK-BE-NEXT: .LBB3_2: @ %for.body ; CHECK-BE-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-BE-NEXT: ldrh lr, [r3, #2]! -; CHECK-BE-NEXT: ldrsh r4, [r2, #2]! -; CHECK-BE-NEXT: ldrsh.w r5, [r3, #2] -; CHECK-BE-NEXT: ldrsh.w r6, [r2, #2] -; CHECK-BE-NEXT: smlabb r4, r4, lr, r12 -; CHECK-BE-NEXT: smlabb r12, r6, r5, r4 ; CHECK-BE-NEXT: subs r0, #1 +; CHECK-BE-NEXT: ldrsh r4, [r2, #2]! +; CHECK-BE-NEXT: ldrsh.w r5, [r2, #2] ; CHECK-BE-NEXT: mul r1, lr, r1 +; CHECK-BE-NEXT: smlabb r12, r4, lr, r12 +; CHECK-BE-NEXT: ldrsh.w r4, [r3, #2] +; CHECK-BE-NEXT: smlabb r12, r5, r4, r12 ; CHECK-BE-NEXT: bne .LBB3_2 ; CHECK-BE-NEXT: @ %bb.3: @ %for.cond.cleanup ; CHECK-BE-NEXT: add.w r0, r12, r1 -; CHECK-BE-NEXT: pop {r4, r5, r6, pc} -; CHECK-BE-NEXT: .p2align 2 +; CHECK-BE-NEXT: pop {r4, r5, r7, pc} ; CHECK-BE-NEXT: .LBB3_4: ; CHECK-BE-NEXT: mov.w r12, #0 ; CHECK-BE-NEXT: movs r1, #0 ; CHECK-BE-NEXT: add.w r0, r12, r1 -; CHECK-BE-NEXT: pop {r4, r5, r6, pc} +; CHECK-BE-NEXT: pop {r4, r5, r7, pc} entry: %cmp24 = icmp sgt i32 %arg, 0 br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup @@ -430,16 +414,15 @@ define i32 @multi_uses(i32 %arg, ptr nocapture readnone %arg1, ptr nocapture rea ; CHECK-LE-NEXT: cmp r0, #1 ; CHECK-LE-NEXT: blt .LBB4_4 ; CHECK-LE-NEXT: @ %bb.1: @ %for.body.preheader -; CHECK-LE-NEXT: subs r2, #2 ; CHECK-LE-NEXT: subs r3, #2 +; CHECK-LE-NEXT: subs r2, #2 ; CHECK-LE-NEXT: mov.w lr, #0 ; CHECK-LE-NEXT: mov.w r12, #0 -; CHECK-LE-NEXT: .p2align 2 ; CHECK-LE-NEXT: .LBB4_2: @ %for.body ; CHECK-LE-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-LE-NEXT: ldr r1, [r3, #2]! -; CHECK-LE-NEXT: ldr r4, [r2, #2]! ; CHECK-LE-NEXT: subs r0, #1 +; CHECK-LE-NEXT: ldr r4, [r2, #2]! ; CHECK-LE-NEXT: smlad lr, r4, r1, lr ; CHECK-LE-NEXT: eor.w r4, r1, r12 ; CHECK-LE-NEXT: mul r1, r4, r1 @@ -448,7 +431,6 @@ define i32 @multi_uses(i32 %arg, ptr nocapture readnone %arg1, ptr nocapture rea ; CHECK-LE-NEXT: @ %bb.3: @ %for.cond.cleanup ; CHECK-LE-NEXT: add.w r0, lr, r12 ; CHECK-LE-NEXT: pop {r4, pc} -; CHECK-LE-NEXT: .p2align 2 ; CHECK-LE-NEXT: .LBB4_4: ; CHECK-LE-NEXT: mov.w lr, #0 ; CHECK-LE-NEXT: mov.w r12, #0 @@ -457,38 +439,36 @@ define i32 @multi_uses(i32 %arg, ptr nocapture readnone %arg1, ptr nocapture rea ; ; CHECK-BE-LABEL: multi_uses: ; CHECK-BE: @ %bb.0: @ %entry -; CHECK-BE-NEXT: .save {r4, r5, r6, lr} -; CHECK-BE-NEXT: push {r4, r5, r6, lr} +; CHECK-BE-NEXT: .save {r4, r5, r7, lr} +; CHECK-BE-NEXT: push {r4, r5, r7, lr} ; CHECK-BE-NEXT: cmp r0, #1 ; CHECK-BE-NEXT: blt .LBB4_4 ; CHECK-BE-NEXT: @ %bb.1: @ %for.body.preheader -; CHECK-BE-NEXT: subs r2, #2 ; CHECK-BE-NEXT: subs r3, #2 +; CHECK-BE-NEXT: subs r2, #2 ; CHECK-BE-NEXT: mov.w r12, #0 ; CHECK-BE-NEXT: mov.w lr, #0 -; CHECK-BE-NEXT: .p2align 2 ; CHECK-BE-NEXT: .LBB4_2: @ %for.body ; CHECK-BE-NEXT: @ =>This Inner Loop Header: Depth=1 -; CHECK-BE-NEXT: ldrsh r1, [r3, #2]! ; CHECK-BE-NEXT: ldrsh r4, [r2, #2]! -; CHECK-BE-NEXT: ldrsh.w r5, [r3, #2] -; CHECK-BE-NEXT: ldrsh.w r6, [r2, #2] -; CHECK-BE-NEXT: smlabb r4, r4, r1, r12 -; CHECK-BE-NEXT: smlabb r12, r6, r5, r4 -; CHECK-BE-NEXT: eor.w r6, r1, lr -; CHECK-BE-NEXT: muls r1, r6, r1 ; CHECK-BE-NEXT: subs r0, #1 +; CHECK-BE-NEXT: ldrsh r1, [r3, #2]! +; CHECK-BE-NEXT: ldrsh.w r5, [r2, #2] +; CHECK-BE-NEXT: smlabb r12, r4, r1, r12 +; CHECK-BE-NEXT: ldrsh.w r4, [r3, #2] +; CHECK-BE-NEXT: smlabb r12, r5, r4, r12 +; CHECK-BE-NEXT: eor.w r5, r1, lr +; CHECK-BE-NEXT: mul r1, r5, r1 ; CHECK-BE-NEXT: lsl.w lr, r1, #16 ; CHECK-BE-NEXT: bne .LBB4_2 ; CHECK-BE-NEXT: @ %bb.3: @ %for.cond.cleanup ; CHECK-BE-NEXT: add.w r0, r12, lr -; CHECK-BE-NEXT: pop {r4, r5, r6, pc} -; CHECK-BE-NEXT: .p2align 2 +; CHECK-BE-NEXT: pop {r4, r5, r7, pc} ; CHECK-BE-NEXT: .LBB4_4: ; CHECK-BE-NEXT: mov.w r12, #0 ; CHECK-BE-NEXT: mov.w lr, #0 ; CHECK-BE-NEXT: add.w r0, r12, lr -; CHECK-BE-NEXT: pop {r4, r5, r6, pc} +; CHECK-BE-NEXT: pop {r4, r5, r7, pc} entry: %cmp24 = icmp sgt i32 %arg, 0 br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/smlad0.ll b/llvm/test/CodeGen/ARM/ParallelDSP/smlad0.ll index 5b2dba4..d9af387 100644 --- a/llvm/test/CodeGen/ARM/ParallelDSP/smlad0.ll +++ b/llvm/test/CodeGen/ARM/ParallelDSP/smlad0.ll @@ -1,11 +1,11 @@ -; RUN: opt -mtriple=arm-none-none-eabi -mcpu=cortex-m33 < %s -arm-parallel-dsp -S | FileCheck %s -; RUN: opt -mtriple=armeb-arm-eabi -mcpu=cortex-m0 < %s -arm-parallel-dsp -S | FileCheck %s --check-prefix=CHECK-UNSUPPORTED +; RUN: opt -mtriple=armv8m.main-none-none-eabi -mattr=+dsp < %s -arm-parallel-dsp -S | FileCheck %s ; ; The Cortex-M0 does not support unaligned accesses: -; RUN: opt -mtriple=arm-none-none-eabi -mcpu=cortex-m0 < %s -arm-parallel-dsp -S | FileCheck %s --check-prefix=CHECK-UNSUPPORTED +; RUN: opt -mtriple=armv6m-none-none-eabi < %s -arm-parallel-dsp -S | FileCheck %s --check-prefix=CHECK-UNSUPPORTED +; RUN: opt -mtriple=armv6meb-none-eabi-eabi < %s -arm-parallel-dsp -S | FileCheck %s --check-prefix=CHECK-UNSUPPORTED ; ; Check DSP extension: -; RUN: opt -mtriple=arm-none-none-eabi -mcpu=cortex-m33 -mattr=-dsp < %s -arm-parallel-dsp -S | FileCheck %s --check-prefix=CHECK-UNSUPPORTED +; RUN: opt -mtriple=armv8m.main-none-none-eabi -mattr=-dsp < %s -arm-parallel-dsp -S | FileCheck %s --check-prefix=CHECK-UNSUPPORTED define dso_local i32 @OneReduction(i32 %arg, ptr nocapture readnone %arg1, ptr nocapture readonly %arg2, ptr nocapture readonly %arg3) { ; diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/smlad1.ll b/llvm/test/CodeGen/ARM/ParallelDSP/smlad1.ll index 1327452..9b61946 100644 --- a/llvm/test/CodeGen/ARM/ParallelDSP/smlad1.ll +++ b/llvm/test/CodeGen/ARM/ParallelDSP/smlad1.ll @@ -1,4 +1,4 @@ -; RUN: opt -mtriple=arm-none-none-eabi -mcpu=cortex-m33 < %s -arm-parallel-dsp -S | FileCheck %s +; RUN: opt -mtriple=armv8m.main-none-none-eabi -mattr=+dsp < %s -arm-parallel-dsp -S | FileCheck %s ; CHECK-LABEL: @test1 ; CHECK: %mac1{{\.}}026 = phi i32 [ [[V8:%[0-9]+]], %for.body ], [ 0, %for.body.preheader ] diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/smlad10.ll b/llvm/test/CodeGen/ARM/ParallelDSP/smlad10.ll index e2b0feb..a3d3fc2 100644 --- a/llvm/test/CodeGen/ARM/ParallelDSP/smlad10.ll +++ b/llvm/test/CodeGen/ARM/ParallelDSP/smlad10.ll @@ -1,4 +1,4 @@ -; RUN: opt -mtriple=arm-none-none-eabi -mcpu=cortex-m33 < %s -arm-parallel-dsp -S | FileCheck %s +; RUN: opt -mtriple=armv8m.main-none-none-eabi -mattr=+dsp < %s -arm-parallel-dsp -S | FileCheck %s ; ; Reduction statement is an i64 type: we only support i32 so check that the ; rewrite isn't triggered. diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/smlad11.ll b/llvm/test/CodeGen/ARM/ParallelDSP/smlad11.ll index 7c1a9bc..061603d 100644 --- a/llvm/test/CodeGen/ARM/ParallelDSP/smlad11.ll +++ b/llvm/test/CodeGen/ARM/ParallelDSP/smlad11.ll @@ -1,5 +1,5 @@ ; REQUIRES: asserts -; RUN: opt -mtriple=arm-none-none-eabi -mcpu=cortex-m33 < %s -arm-parallel-dsp -S -stats 2>&1 | FileCheck %s +; RUN: opt -mtriple=armv8m.main-none-none-eabi -mattr=+dsp < %s -arm-parallel-dsp -S -stats 2>&1 | FileCheck %s ; ; A more complicated chain: 4 mul operations, so we expect 2 smlad calls. ; diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/smlad12.ll b/llvm/test/CodeGen/ARM/ParallelDSP/smlad12.ll index a967626..480af89 100644 --- a/llvm/test/CodeGen/ARM/ParallelDSP/smlad12.ll +++ b/llvm/test/CodeGen/ARM/ParallelDSP/smlad12.ll @@ -1,4 +1,4 @@ -; RUN: opt -mtriple=arm-none-none-eabi -mcpu=cortex-m33 < %s -arm-parallel-dsp -S | FileCheck %s +; RUN: opt -mtriple=armv8m.main-none-none-eabi -mattr=+dsp < %s -arm-parallel-dsp -S | FileCheck %s ; ; The loop header is not the loop latch. ; diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/smlad2.ll b/llvm/test/CodeGen/ARM/ParallelDSP/smlad2.ll index ac0f75e..da36338 100644 --- a/llvm/test/CodeGen/ARM/ParallelDSP/smlad2.ll +++ b/llvm/test/CodeGen/ARM/ParallelDSP/smlad2.ll @@ -1,4 +1,4 @@ -; RUN: opt -mtriple=arm-none-none-eabi -mcpu=cortex-m33 < %s -arm-parallel-dsp -S | FileCheck %s +; RUN: opt -mtriple=armv8m.main-none-none-eabi -mattr=+dsp < %s -arm-parallel-dsp -S | FileCheck %s ; ; Operands of both muls are not symmetrical (see also comments inlined below), check ; that the rewrite isn't triggered. diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/smlad3.ll b/llvm/test/CodeGen/ARM/ParallelDSP/smlad3.ll index 73a04a3..b7b4b55 100644 --- a/llvm/test/CodeGen/ARM/ParallelDSP/smlad3.ll +++ b/llvm/test/CodeGen/ARM/ParallelDSP/smlad3.ll @@ -1,4 +1,4 @@ -; RUN: opt -mtriple=arm-none-none-eabi -mcpu=cortex-m33 < %s -arm-parallel-dsp -S | FileCheck %s +; RUN: opt -mtriple=armv8m.main-none-none-eabi -mattr=+dsp < %s -arm-parallel-dsp -S | FileCheck %s ; ; The loads are not consecutive: check that the rewrite isn't triggered. ; diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/smlad4.ll b/llvm/test/CodeGen/ARM/ParallelDSP/smlad4.ll index a89c7d4..f74d1ac 100644 --- a/llvm/test/CodeGen/ARM/ParallelDSP/smlad4.ll +++ b/llvm/test/CodeGen/ARM/ParallelDSP/smlad4.ll @@ -1,4 +1,4 @@ -; RUN: opt -mtriple=arm-none-none-eabi -mcpu=cortex-m33 < %s -arm-parallel-dsp -S | FileCheck %s +; RUN: opt -mtriple=armv8m.main-none-none-eabi -mattr=+dsp < %s -arm-parallel-dsp -S | FileCheck %s ; ; The loads are not narrow loads: check that the rewrite isn't triggered. ; diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/smlad5.ll b/llvm/test/CodeGen/ARM/ParallelDSP/smlad5.ll index 298afe3..b6166d9 100644 --- a/llvm/test/CodeGen/ARM/ParallelDSP/smlad5.ll +++ b/llvm/test/CodeGen/ARM/ParallelDSP/smlad5.ll @@ -1,4 +1,4 @@ -; RUN: opt -mtriple=arm-none-none-eabi -mcpu=cortex-m33 < %s -arm-parallel-dsp -S | FileCheck %s +; RUN: opt -mtriple=armv8m.main-none-none-eabi -mattr=+dsp < %s -arm-parallel-dsp -S | FileCheck %s ; ; The loads are volatile loads: check that the rewrite isn't triggered. ; diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/smlad8.ll b/llvm/test/CodeGen/ARM/ParallelDSP/smlad8.ll index bfa154c..a3acef4 100644 --- a/llvm/test/CodeGen/ARM/ParallelDSP/smlad8.ll +++ b/llvm/test/CodeGen/ARM/ParallelDSP/smlad8.ll @@ -1,4 +1,4 @@ -; RUN: opt -mtriple=arm-none-none-eabi -mcpu=cortex-m33 < %s -arm-parallel-dsp -S | FileCheck %s +; RUN: opt -mtriple=armv8m.main-none-none-eabi -mattr=+dsp < %s -arm-parallel-dsp -S | FileCheck %s ; ; Mul with operands that are not simple load and sext/zext chains: this is not ; yet supported so the rewrite shouldn't trigger (but we do want to support this diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/smlad9.ll b/llvm/test/CodeGen/ARM/ParallelDSP/smlad9.ll index 0c33d93..b33091e 100644 --- a/llvm/test/CodeGen/ARM/ParallelDSP/smlad9.ll +++ b/llvm/test/CodeGen/ARM/ParallelDSP/smlad9.ll @@ -1,4 +1,4 @@ -; RUN: opt -mtriple=arm-none-none-eabi -mcpu=cortex-m33 < %s -arm-parallel-dsp -S | FileCheck %s +; RUN: opt -mtriple=armv8m.main-none-none-eabi -mattr=+dsp < %s -arm-parallel-dsp -S | FileCheck %s ; ; Muls with operands that are constants: not yet supported, so the rewrite ; should not trigger (but we do want to add this soon). diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/smladx-1.ll b/llvm/test/CodeGen/ARM/ParallelDSP/smladx-1.ll index 55328ab..c770546 100644 --- a/llvm/test/CodeGen/ARM/ParallelDSP/smladx-1.ll +++ b/llvm/test/CodeGen/ARM/ParallelDSP/smladx-1.ll @@ -1,7 +1,7 @@ -; RUN: opt -mtriple=thumbv8m.main -mcpu=cortex-m33 -arm-parallel-dsp %s -S -o - | FileCheck %s -; RUN: opt -mtriple=arm-none-none-eabi -mcpu=cortex-m0 < %s -arm-parallel-dsp -S | FileCheck %s --check-prefix=CHECK-UNSUPPORTED -; RUN: opt -mtriple=arm-none-none-eabi -mcpu=cortex-m33 -mattr=-dsp < %s -arm-parallel-dsp -S | FileCheck %s --check-prefix=CHECK-UNSUPPORTED -; RUN: opt -mtriple=armeb-arm-eabi -mcpu=cortex-m33 < %s -arm-parallel-dsp -S | FileCheck %s --check-prefix=CHECK-UNSUPPORTED +; RUN: opt -mtriple=armv8m.main-none-none-eabi -mattr=+dsp -arm-parallel-dsp %s -S -o - | FileCheck %s +; RUN: opt -mtriple=armv6m-none-none-eabi < %s -arm-parallel-dsp -S | FileCheck %s --check-prefix=CHECK-UNSUPPORTED +; RUN: opt -mtriple=armv8m.main-none-none-eabi -mattr=-dsp < %s -arm-parallel-dsp -S | FileCheck %s --check-prefix=CHECK-UNSUPPORTED +; RUN: opt -mtriple=armv8m.maineb-none-none-eabi -mattr=+dsp < %s -arm-parallel-dsp -S | FileCheck %s --check-prefix=CHECK-UNSUPPORTED define i32 @smladx(ptr nocapture readonly %pIn1, ptr nocapture readonly %pIn2, i32 %j, i32 %limit) { diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/smlald0.ll b/llvm/test/CodeGen/ARM/ParallelDSP/smlald0.ll index fca5b76..843776f 100644 --- a/llvm/test/CodeGen/ARM/ParallelDSP/smlald0.ll +++ b/llvm/test/CodeGen/ARM/ParallelDSP/smlald0.ll @@ -1,11 +1,11 @@ -; RUN: opt -mtriple=arm-none-none-eabi -mcpu=cortex-m33 < %s -arm-parallel-dsp -S | FileCheck %s -; RUN: opt -mtriple=armeb-none-none-eabi -mcpu=cortex-m33 < %s -arm-parallel-dsp -S | FileCheck %s --check-prefix=CHECK-UNSUPPORTED +; RUN: opt -mtriple=armv8m.main-none-none-eabi -mattr=+dsp < %s -arm-parallel-dsp -S | FileCheck %s +; RUN: opt -mtriple=armv8m.maineb-none-none-eabi -mattr=+dsp < %s -arm-parallel-dsp -S | FileCheck %s --check-prefix=CHECK-UNSUPPORTED ; ; The Cortex-M0 does not support unaligned accesses: -; RUN: opt -mtriple=arm-none-none-eabi -mcpu=cortex-m0 < %s -arm-parallel-dsp -S | FileCheck %s --check-prefix=CHECK-UNSUPPORTED +; RUN: opt -mtriple=armv6m-none-none-eabi < %s -arm-parallel-dsp -S | FileCheck %s --check-prefix=CHECK-UNSUPPORTED ; ; Check DSP extension: -; RUN: opt -mtriple=arm-none-none-eabi -mcpu=cortex-m33 -mattr=-dsp < %s -arm-parallel-dsp -S | FileCheck %s --check-prefix=CHECK-UNSUPPORTED +; RUN: opt -mtriple=armv8m.main-none-none-eabi -mattr=-dsp < %s -arm-parallel-dsp -S | FileCheck %s --check-prefix=CHECK-UNSUPPORTED define dso_local i64 @OneReduction(i32 %arg, ptr nocapture readnone %arg1, ptr nocapture readonly %arg2, ptr nocapture readonly %arg3) { ; diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/smlald1.ll b/llvm/test/CodeGen/ARM/ParallelDSP/smlald1.ll index 2ab6d71..63acd933 100644 --- a/llvm/test/CodeGen/ARM/ParallelDSP/smlald1.ll +++ b/llvm/test/CodeGen/ARM/ParallelDSP/smlald1.ll @@ -1,4 +1,4 @@ -; RUN: opt -mtriple=arm-none-none-eabi -mcpu=cortex-m33 < %s -arm-parallel-dsp -S | FileCheck %s +; RUN: opt -mtriple=armv8m.main-none-none-eabi -mattr=+dsp < %s -arm-parallel-dsp -S | FileCheck %s ; CHECK-LABEL: @test1 ; CHECK: %mac1{{\.}}026 = phi i64 [ [[V8:%[0-9]+]], %for.body ], [ 0, %for.body.preheader ] diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/smlald2.ll b/llvm/test/CodeGen/ARM/ParallelDSP/smlald2.ll index 13c9199..9d721ac 100644 --- a/llvm/test/CodeGen/ARM/ParallelDSP/smlald2.ll +++ b/llvm/test/CodeGen/ARM/ParallelDSP/smlald2.ll @@ -1,10 +1,10 @@ -; RUN: opt -mtriple=arm-none-none-eabi -mcpu=cortex-m33 < %s -arm-parallel-dsp -S | FileCheck %s +; RUN: opt -mtriple=armv8m.main-none-none-eabi -mattr=+dsp < %s -arm-parallel-dsp -S | FileCheck %s ; ; The Cortex-M0 does not support unaligned accesses: -; RUN: opt -mtriple=arm-none-none-eabi -mcpu=cortex-m0 < %s -arm-parallel-dsp -S | FileCheck %s --check-prefix=CHECK-UNSUPPORTED +; RUN: opt -mtriple=armv6m-none-none-eabi < %s -arm-parallel-dsp -S | FileCheck %s --check-prefix=CHECK-UNSUPPORTED ; ; Check DSP extension: -; RUN: opt -mtriple=arm-none-none-eabi -mcpu=cortex-m33 -mattr=-dsp < %s -arm-parallel-dsp -S | FileCheck %s --check-prefix=CHECK-UNSUPPORTED +; RUN: opt -mtriple=armv8m.main-none-none-eabi -mattr=-dsp < %s -arm-parallel-dsp -S | FileCheck %s --check-prefix=CHECK-UNSUPPORTED define dso_local i64 @OneReduction(i32 %arg, ptr nocapture readnone %arg1, ptr nocapture readonly %arg2, ptr nocapture readonly %arg3) { ; diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/smlaldx-1.ll b/llvm/test/CodeGen/ARM/ParallelDSP/smlaldx-1.ll index a24fbfd..d6a18bc 100644 --- a/llvm/test/CodeGen/ARM/ParallelDSP/smlaldx-1.ll +++ b/llvm/test/CodeGen/ARM/ParallelDSP/smlaldx-1.ll @@ -1,6 +1,6 @@ -; RUN: opt -mtriple=thumbv8m.main -mcpu=cortex-m33 -arm-parallel-dsp %s -S -o - | FileCheck %s -; RUN: opt -mtriple=arm-none-none-eabi -mcpu=cortex-m0 < %s -arm-parallel-dsp -S | FileCheck %s --check-prefix=CHECK-UNSUPPORTED -; RUN: opt -mtriple=arm-none-none-eabi -mcpu=cortex-m33 -mattr=-dsp < %s -arm-parallel-dsp -S | FileCheck %s --check-prefix=CHECK-UNSUPPORTED +; RUN: opt -mtriple=armv8m.main-none-none-eabi -mattr=+dsp -arm-parallel-dsp %s -S -o - | FileCheck %s +; RUN: opt -mtriple=armv6m-none-none-eabi < %s -arm-parallel-dsp -S | FileCheck %s --check-prefix=CHECK-UNSUPPORTED +; RUN: opt -mtriple=armv8m.main-none-none-eabi -mattr=-dsp < %s -arm-parallel-dsp -S | FileCheck %s --check-prefix=CHECK-UNSUPPORTED define i64 @smlaldx(ptr nocapture readonly %pIn1, ptr nocapture readonly %pIn2, i32 %j, i32 %limit) { diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/smlaldx-2.ll b/llvm/test/CodeGen/ARM/ParallelDSP/smlaldx-2.ll index 7158846..e47cf75 100644 --- a/llvm/test/CodeGen/ARM/ParallelDSP/smlaldx-2.ll +++ b/llvm/test/CodeGen/ARM/ParallelDSP/smlaldx-2.ll @@ -1,6 +1,6 @@ -; RUN: opt -mtriple=thumbv8m.main -mcpu=cortex-m33 -arm-parallel-dsp %s -S -o - | FileCheck %s -; RUN: opt -mtriple=arm-none-none-eabi -mcpu=cortex-m0 < %s -arm-parallel-dsp -S | FileCheck %s --check-prefix=CHECK-UNSUPPORTED -; RUN: opt -mtriple=arm-none-none-eabi -mcpu=cortex-m33 -mattr=-dsp < %s -arm-parallel-dsp -S | FileCheck %s --check-prefix=CHECK-UNSUPPORTED +; RUN: opt -mtriple=armv8m.main-none-none-eabi -mattr=+dsp -arm-parallel-dsp %s -S -o - | FileCheck %s +; RUN: opt -mtriple=armv6m-none-none-eabi < %s -arm-parallel-dsp -S | FileCheck %s --check-prefix=CHECK-UNSUPPORTED +; RUN: opt -mtriple=armv8m.main-none-none-eabi -mattr=-dsp < %s -arm-parallel-dsp -S | FileCheck %s --check-prefix=CHECK-UNSUPPORTED define i64 @smlaldx(ptr nocapture readonly %pIn1, ptr nocapture readonly %pIn2, i32 %j, i32 %limit) { -- 2.7.4