From 9bb18a4f9ee300b566e642e6960479b63cf8f011 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marcin=20=C5=9Alusarz?= Date: Thu, 12 Jan 2023 16:06:42 +0100 Subject: [PATCH] intel/compiler: fix generation of vec8/vec16 alu instruction I stumbled on this when I inserted some suboptimal lowering code after all optimizations. Adding certain subset of optimizations after my lowering code actually avoided this bug, so I think it's not possible to hit this on upstream. Let's fix this for the next person generating suboptimal code... Reviewed-by: Sagar Ghuge Reviewed-by: Lionel Landwerlin Part-of: --- src/intel/compiler/brw_fs_nir.cpp | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index bed647e..8da05b8 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -1019,7 +1019,9 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr, } } - for (unsigned i = 0; i < 4; i++) { + unsigned last_bit = util_last_bit(instr->dest.write_mask); + + for (unsigned i = 0; i < last_bit; i++) { if (!(instr->dest.write_mask & (1 << i))) continue; @@ -1037,7 +1039,7 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr, * any swizzling. */ if (need_extra_copy) { - for (unsigned i = 0; i < 4; i++) { + for (unsigned i = 0; i < last_bit; i++) { if (!(instr->dest.write_mask & (1 << i))) continue; -- 2.7.4