From 9ba44da833a15ac2296b75b8fd6b2eafe17c9cd5 Mon Sep 17 00:00:00 2001
From: Tom Stellard <thomas.stellard@amd.com>
Date: Sat, 27 Jul 2013 02:54:44 +0000
Subject: [PATCH] SimplifyCFG: Add missing tests from r187278

llvm-svn: 187291
---
 .../test/Transforms/SimplifyCFG/R600/lit.local.cfg |  6 +++
 .../SimplifyCFG/R600/parallelandifcollapse.ll      | 63 ++++++++++++++++++++++
 .../SimplifyCFG/R600/parallelorifcollapse.ll       | 56 +++++++++++++++++++
 3 files changed, 125 insertions(+)
 create mode 100644 llvm/test/Transforms/SimplifyCFG/R600/lit.local.cfg
 create mode 100644 llvm/test/Transforms/SimplifyCFG/R600/parallelandifcollapse.ll
 create mode 100644 llvm/test/Transforms/SimplifyCFG/R600/parallelorifcollapse.ll

diff --git a/llvm/test/Transforms/SimplifyCFG/R600/lit.local.cfg b/llvm/test/Transforms/SimplifyCFG/R600/lit.local.cfg
new file mode 100644
index 0000000..4f6e579
--- /dev/null
+++ b/llvm/test/Transforms/SimplifyCFG/R600/lit.local.cfg
@@ -0,0 +1,6 @@
+config.suffixes = ['.ll', '.c', '.cpp']
+
+targets = set(config.root.targets_to_build.split())
+if not 'R600' in targets:
+    config.unsupported = True
+
diff --git a/llvm/test/Transforms/SimplifyCFG/R600/parallelandifcollapse.ll b/llvm/test/Transforms/SimplifyCFG/R600/parallelandifcollapse.ll
new file mode 100644
index 0000000..053921c
--- /dev/null
+++ b/llvm/test/Transforms/SimplifyCFG/R600/parallelandifcollapse.ll
@@ -0,0 +1,63 @@
+; Function Attrs: nounwind
+; RUN: opt < %s -mtriple=r600-unknown-linux-gnu -optimizecfg -basicaa -S | FileCheck %s
+;
+; CFG optimization should use parallel-and mode to generate branch conditions and
+; then merge if-regions with the same bodies, which should result in 2 branches.
+; To see the assembly output without this transformation, remove -basicaa option.
+; 
+; CHECK: or i1
+; CHECK-NEXT: br
+; CHECK: br
+; CHECK: ret
+define void @_Z9chk1D_512v() #0 {
+entry:
+  %a0 = alloca i32, align 4
+  %b0 = alloca i32, align 4
+  %c0 = alloca i32, align 4
+  %d0 = alloca i32, align 4
+  %a1 = alloca i32, align 4
+  %b1 = alloca i32, align 4
+  %c1 = alloca i32, align 4
+  %d1 = alloca i32, align 4
+  %data = alloca i32, align 4
+  %0 = load i32* %a0, align 4
+  %1 = load i32* %b0, align 4
+  %cmp = icmp ne i32 %0, %1
+  br i1 %cmp, label %land.lhs.true, label %if.else
+
+land.lhs.true:                                    ; preds = %entry
+  %2 = load i32* %c0, align 4
+  %3 = load i32* %d0, align 4
+  %cmp1 = icmp ne i32 %2, %3
+  br i1 %cmp1, label %if.then, label %if.else
+
+if.then:                                          ; preds = %land.lhs.true
+  br label %if.end
+
+if.else:                                          ; preds = %land.lhs.true, %entry
+  store i32 1, i32* %data, align 4
+  br label %if.end
+
+if.end:                                           ; preds = %if.else, %if.then
+  %4 = load i32* %a1, align 4
+  %5 = load i32* %b1, align 4
+  %cmp2 = icmp ne i32 %4, %5
+  br i1 %cmp2, label %land.lhs.true3, label %if.else6
+
+land.lhs.true3:                                   ; preds = %if.end
+  %6 = load i32* %c1, align 4
+  %7 = load i32* %d1, align 4
+  %cmp4 = icmp ne i32 %6, %7
+  br i1 %cmp4, label %if.then5, label %if.else6
+
+if.then5:                                         ; preds = %land.lhs.true3
+  br label %if.end7
+
+if.else6:                                         ; preds = %land.lhs.true3, %if.end
+  store i32 1, i32* %data, align 4
+  br label %if.end7
+
+if.end7:                                          ; preds = %if.else6, %if.then5
+  ret void
+}
+
diff --git a/llvm/test/Transforms/SimplifyCFG/R600/parallelorifcollapse.ll b/llvm/test/Transforms/SimplifyCFG/R600/parallelorifcollapse.ll
new file mode 100644
index 0000000..e1bb5fc
--- /dev/null
+++ b/llvm/test/Transforms/SimplifyCFG/R600/parallelorifcollapse.ll
@@ -0,0 +1,56 @@
+; Function Attrs: nounwind
+; RUN: opt < %s -mtriple=r600-unknown-linux-gnu -optimizecfg -basicaa -S | FileCheck %s
+;
+; CFG optimization should use parallel-or mode to generate branch conditions and
+; then merge if-regions with the same bodies, which should result in 2 branches.
+; To see the assembly output without this transformation, remove -basicaa option.
+;
+; CHECK: or i1
+; CHECK-NEXT: br
+; CHECK: br
+; CHECK: ret
+define void @_Z9chk1D_512v() #0 {
+entry:
+  %a0 = alloca i32, align 4
+  %b0 = alloca i32, align 4
+  %c0 = alloca i32, align 4
+  %d0 = alloca i32, align 4
+  %a1 = alloca i32, align 4
+  %b1 = alloca i32, align 4
+  %c1 = alloca i32, align 4
+  %d1 = alloca i32, align 4
+  %data = alloca i32, align 4
+  %0 = load i32* %a0, align 4
+  %1 = load i32* %b0, align 4
+  %cmp = icmp ne i32 %0, %1
+  br i1 %cmp, label %land.lhs.true, label %if.end
+
+land.lhs.true:                                    ; preds = %entry
+  %2 = load i32* %c0, align 4
+  %3 = load i32* %d0, align 4
+  %cmp1 = icmp ne i32 %2, %3
+  br i1 %cmp1, label %if.then, label %if.end
+
+if.then:                                          ; preds = %land.lhs.true
+  store i32 1, i32* %data, align 4
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %land.lhs.true, %entry
+  %4 = load i32* %a1, align 4
+  %5 = load i32* %b1, align 4
+  %cmp2 = icmp ne i32 %4, %5
+  br i1 %cmp2, label %land.lhs.true3, label %if.end6
+
+land.lhs.true3:                                   ; preds = %if.end
+  %6 = load i32* %c1, align 4
+  %7 = load i32* %d1, align 4
+  %cmp4 = icmp ne i32 %6, %7
+  br i1 %cmp4, label %if.then5, label %if.end6
+
+if.then5:                                         ; preds = %land.lhs.true3
+  store i32 1, i32* %data, align 4
+  br label %if.end6
+
+if.end6:                                          ; preds = %if.then5, %land.lhs.true3, %if.end
+  ret void
+}
-- 
2.7.4