From 9b59207a985026c989cd6afb7c34e3926436ddb1 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Wed, 28 Dec 2022 15:16:13 -0800 Subject: [PATCH] [RISCV] Fix mistakes in fixed-vectors-vreductions-mask.ll command lines. NFC There were 4 RUN lines, but only 2 of them were unique. I believe we were trying to test LMUL=1 and LMUL=8 with riscv32 and riscv64. But put riscv32 on both LMUL=1 lines and riscv64 on both LMUL=8 lines. --- .../RISCV/rvv/fixed-vectors-vreductions-mask.ll | 1020 +++++++++++++------- 1 file changed, 692 insertions(+), 328 deletions(-) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll index e00b182..28e4c74 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll @@ -1,31 +1,51 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 -; RUN: llc -mtriple=riscv32 -mattr=+m,+v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 -; RUN: llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8 -; RUN: llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8 +; RUN: llc -mtriple=riscv32 -mattr=+m,+v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1,LMULMAX1-RV32 +; RUN: llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1,LMULMAX1-RV64 +; RUN: llc -mtriple=riscv32 -mattr=+m,+v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8,LMULMAX8-RV32 +; RUN: llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8,LMULMAX8-RV64 declare i1 @llvm.vector.reduce.or.v1i1(<1 x i1>) define signext i1 @vreduce_or_v1i1(<1 x i1> %v) { -; LMULMAX1-LABEL: vreduce_or_v1i1: -; LMULMAX1: # %bb.0: -; LMULMAX1-NEXT: vsetvli a0, zero, e8, mf8, ta, ma -; LMULMAX1-NEXT: vmv.v.i v8, 0 -; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0 -; LMULMAX1-NEXT: vmv.x.s a0, v8 -; LMULMAX1-NEXT: slli a0, a0, 31 -; LMULMAX1-NEXT: srai a0, a0, 31 -; LMULMAX1-NEXT: ret +; LMULMAX1-RV32-LABEL: vreduce_or_v1i1: +; LMULMAX1-RV32: # %bb.0: +; LMULMAX1-RV32-NEXT: vsetvli a0, zero, e8, mf8, ta, ma +; LMULMAX1-RV32-NEXT: vmv.v.i v8, 0 +; LMULMAX1-RV32-NEXT: vmerge.vim v8, v8, 1, v0 +; LMULMAX1-RV32-NEXT: vmv.x.s a0, v8 +; LMULMAX1-RV32-NEXT: slli a0, a0, 31 +; LMULMAX1-RV32-NEXT: srai a0, a0, 31 +; LMULMAX1-RV32-NEXT: ret ; -; LMULMAX8-LABEL: vreduce_or_v1i1: -; LMULMAX8: # %bb.0: -; LMULMAX8-NEXT: vsetvli a0, zero, e8, mf8, ta, ma -; LMULMAX8-NEXT: vmv.v.i v8, 0 -; LMULMAX8-NEXT: vmerge.vim v8, v8, 1, v0 -; LMULMAX8-NEXT: vmv.x.s a0, v8 -; LMULMAX8-NEXT: slli a0, a0, 63 -; LMULMAX8-NEXT: srai a0, a0, 63 -; LMULMAX8-NEXT: ret +; LMULMAX1-RV64-LABEL: vreduce_or_v1i1: +; LMULMAX1-RV64: # %bb.0: +; LMULMAX1-RV64-NEXT: vsetvli a0, zero, e8, mf8, ta, ma +; LMULMAX1-RV64-NEXT: vmv.v.i v8, 0 +; LMULMAX1-RV64-NEXT: vmerge.vim v8, v8, 1, v0 +; LMULMAX1-RV64-NEXT: vmv.x.s a0, v8 +; LMULMAX1-RV64-NEXT: slli a0, a0, 63 +; LMULMAX1-RV64-NEXT: srai a0, a0, 63 +; LMULMAX1-RV64-NEXT: ret +; +; LMULMAX8-RV32-LABEL: vreduce_or_v1i1: +; LMULMAX8-RV32: # %bb.0: +; LMULMAX8-RV32-NEXT: vsetvli a0, zero, e8, mf8, ta, ma +; LMULMAX8-RV32-NEXT: vmv.v.i v8, 0 +; LMULMAX8-RV32-NEXT: vmerge.vim v8, v8, 1, v0 +; LMULMAX8-RV32-NEXT: vmv.x.s a0, v8 +; LMULMAX8-RV32-NEXT: slli a0, a0, 31 +; LMULMAX8-RV32-NEXT: srai a0, a0, 31 +; LMULMAX8-RV32-NEXT: ret +; +; LMULMAX8-RV64-LABEL: vreduce_or_v1i1: +; LMULMAX8-RV64: # %bb.0: +; LMULMAX8-RV64-NEXT: vsetvli a0, zero, e8, mf8, ta, ma +; LMULMAX8-RV64-NEXT: vmv.v.i v8, 0 +; LMULMAX8-RV64-NEXT: vmerge.vim v8, v8, 1, v0 +; LMULMAX8-RV64-NEXT: vmv.x.s a0, v8 +; LMULMAX8-RV64-NEXT: slli a0, a0, 63 +; LMULMAX8-RV64-NEXT: srai a0, a0, 63 +; LMULMAX8-RV64-NEXT: ret %red = call i1 @llvm.vector.reduce.or.v1i1(<1 x i1> %v) ret i1 %red } @@ -33,25 +53,45 @@ define signext i1 @vreduce_or_v1i1(<1 x i1> %v) { declare i1 @llvm.vector.reduce.xor.v1i1(<1 x i1>) define signext i1 @vreduce_xor_v1i1(<1 x i1> %v) { -; LMULMAX1-LABEL: vreduce_xor_v1i1: -; LMULMAX1: # %bb.0: -; LMULMAX1-NEXT: vsetvli a0, zero, e8, mf8, ta, ma -; LMULMAX1-NEXT: vmv.v.i v8, 0 -; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0 -; LMULMAX1-NEXT: vmv.x.s a0, v8 -; LMULMAX1-NEXT: slli a0, a0, 31 -; LMULMAX1-NEXT: srai a0, a0, 31 -; LMULMAX1-NEXT: ret +; LMULMAX1-RV32-LABEL: vreduce_xor_v1i1: +; LMULMAX1-RV32: # %bb.0: +; LMULMAX1-RV32-NEXT: vsetvli a0, zero, e8, mf8, ta, ma +; LMULMAX1-RV32-NEXT: vmv.v.i v8, 0 +; LMULMAX1-RV32-NEXT: vmerge.vim v8, v8, 1, v0 +; LMULMAX1-RV32-NEXT: vmv.x.s a0, v8 +; LMULMAX1-RV32-NEXT: slli a0, a0, 31 +; LMULMAX1-RV32-NEXT: srai a0, a0, 31 +; LMULMAX1-RV32-NEXT: ret ; -; LMULMAX8-LABEL: vreduce_xor_v1i1: -; LMULMAX8: # %bb.0: -; LMULMAX8-NEXT: vsetvli a0, zero, e8, mf8, ta, ma -; LMULMAX8-NEXT: vmv.v.i v8, 0 -; LMULMAX8-NEXT: vmerge.vim v8, v8, 1, v0 -; LMULMAX8-NEXT: vmv.x.s a0, v8 -; LMULMAX8-NEXT: slli a0, a0, 63 -; LMULMAX8-NEXT: srai a0, a0, 63 -; LMULMAX8-NEXT: ret +; LMULMAX1-RV64-LABEL: vreduce_xor_v1i1: +; LMULMAX1-RV64: # %bb.0: +; LMULMAX1-RV64-NEXT: vsetvli a0, zero, e8, mf8, ta, ma +; LMULMAX1-RV64-NEXT: vmv.v.i v8, 0 +; LMULMAX1-RV64-NEXT: vmerge.vim v8, v8, 1, v0 +; LMULMAX1-RV64-NEXT: vmv.x.s a0, v8 +; LMULMAX1-RV64-NEXT: slli a0, a0, 63 +; LMULMAX1-RV64-NEXT: srai a0, a0, 63 +; LMULMAX1-RV64-NEXT: ret +; +; LMULMAX8-RV32-LABEL: vreduce_xor_v1i1: +; LMULMAX8-RV32: # %bb.0: +; LMULMAX8-RV32-NEXT: vsetvli a0, zero, e8, mf8, ta, ma +; LMULMAX8-RV32-NEXT: vmv.v.i v8, 0 +; LMULMAX8-RV32-NEXT: vmerge.vim v8, v8, 1, v0 +; LMULMAX8-RV32-NEXT: vmv.x.s a0, v8 +; LMULMAX8-RV32-NEXT: slli a0, a0, 31 +; LMULMAX8-RV32-NEXT: srai a0, a0, 31 +; LMULMAX8-RV32-NEXT: ret +; +; LMULMAX8-RV64-LABEL: vreduce_xor_v1i1: +; LMULMAX8-RV64: # %bb.0: +; LMULMAX8-RV64-NEXT: vsetvli a0, zero, e8, mf8, ta, ma +; LMULMAX8-RV64-NEXT: vmv.v.i v8, 0 +; LMULMAX8-RV64-NEXT: vmerge.vim v8, v8, 1, v0 +; LMULMAX8-RV64-NEXT: vmv.x.s a0, v8 +; LMULMAX8-RV64-NEXT: slli a0, a0, 63 +; LMULMAX8-RV64-NEXT: srai a0, a0, 63 +; LMULMAX8-RV64-NEXT: ret %red = call i1 @llvm.vector.reduce.xor.v1i1(<1 x i1> %v) ret i1 %red } @@ -59,25 +99,45 @@ define signext i1 @vreduce_xor_v1i1(<1 x i1> %v) { declare i1 @llvm.vector.reduce.and.v1i1(<1 x i1>) define signext i1 @vreduce_and_v1i1(<1 x i1> %v) { -; LMULMAX1-LABEL: vreduce_and_v1i1: -; LMULMAX1: # %bb.0: -; LMULMAX1-NEXT: vsetvli a0, zero, e8, mf8, ta, ma -; LMULMAX1-NEXT: vmv.v.i v8, 0 -; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0 -; LMULMAX1-NEXT: vmv.x.s a0, v8 -; LMULMAX1-NEXT: slli a0, a0, 31 -; LMULMAX1-NEXT: srai a0, a0, 31 -; LMULMAX1-NEXT: ret +; LMULMAX1-RV32-LABEL: vreduce_and_v1i1: +; LMULMAX1-RV32: # %bb.0: +; LMULMAX1-RV32-NEXT: vsetvli a0, zero, e8, mf8, ta, ma +; LMULMAX1-RV32-NEXT: vmv.v.i v8, 0 +; LMULMAX1-RV32-NEXT: vmerge.vim v8, v8, 1, v0 +; LMULMAX1-RV32-NEXT: vmv.x.s a0, v8 +; LMULMAX1-RV32-NEXT: slli a0, a0, 31 +; LMULMAX1-RV32-NEXT: srai a0, a0, 31 +; LMULMAX1-RV32-NEXT: ret ; -; LMULMAX8-LABEL: vreduce_and_v1i1: -; LMULMAX8: # %bb.0: -; LMULMAX8-NEXT: vsetvli a0, zero, e8, mf8, ta, ma -; LMULMAX8-NEXT: vmv.v.i v8, 0 -; LMULMAX8-NEXT: vmerge.vim v8, v8, 1, v0 -; LMULMAX8-NEXT: vmv.x.s a0, v8 -; LMULMAX8-NEXT: slli a0, a0, 63 -; LMULMAX8-NEXT: srai a0, a0, 63 -; LMULMAX8-NEXT: ret +; LMULMAX1-RV64-LABEL: vreduce_and_v1i1: +; LMULMAX1-RV64: # %bb.0: +; LMULMAX1-RV64-NEXT: vsetvli a0, zero, e8, mf8, ta, ma +; LMULMAX1-RV64-NEXT: vmv.v.i v8, 0 +; LMULMAX1-RV64-NEXT: vmerge.vim v8, v8, 1, v0 +; LMULMAX1-RV64-NEXT: vmv.x.s a0, v8 +; LMULMAX1-RV64-NEXT: slli a0, a0, 63 +; LMULMAX1-RV64-NEXT: srai a0, a0, 63 +; LMULMAX1-RV64-NEXT: ret +; +; LMULMAX8-RV32-LABEL: vreduce_and_v1i1: +; LMULMAX8-RV32: # %bb.0: +; LMULMAX8-RV32-NEXT: vsetvli a0, zero, e8, mf8, ta, ma +; LMULMAX8-RV32-NEXT: vmv.v.i v8, 0 +; LMULMAX8-RV32-NEXT: vmerge.vim v8, v8, 1, v0 +; LMULMAX8-RV32-NEXT: vmv.x.s a0, v8 +; LMULMAX8-RV32-NEXT: slli a0, a0, 31 +; LMULMAX8-RV32-NEXT: srai a0, a0, 31 +; LMULMAX8-RV32-NEXT: ret +; +; LMULMAX8-RV64-LABEL: vreduce_and_v1i1: +; LMULMAX8-RV64: # %bb.0: +; LMULMAX8-RV64-NEXT: vsetvli a0, zero, e8, mf8, ta, ma +; LMULMAX8-RV64-NEXT: vmv.v.i v8, 0 +; LMULMAX8-RV64-NEXT: vmerge.vim v8, v8, 1, v0 +; LMULMAX8-RV64-NEXT: vmv.x.s a0, v8 +; LMULMAX8-RV64-NEXT: slli a0, a0, 63 +; LMULMAX8-RV64-NEXT: srai a0, a0, 63 +; LMULMAX8-RV64-NEXT: ret %red = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> %v) ret i1 %red } @@ -85,25 +145,45 @@ define signext i1 @vreduce_and_v1i1(<1 x i1> %v) { declare i1 @llvm.vector.reduce.umax.v1i1(<1 x i1>) define signext i1 @vreduce_umax_v1i1(<1 x i1> %v) { -; LMULMAX1-LABEL: vreduce_umax_v1i1: -; LMULMAX1: # %bb.0: -; LMULMAX1-NEXT: vsetvli a0, zero, e8, mf8, ta, ma -; LMULMAX1-NEXT: vmv.v.i v8, 0 -; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0 -; LMULMAX1-NEXT: vmv.x.s a0, v8 -; LMULMAX1-NEXT: slli a0, a0, 31 -; LMULMAX1-NEXT: srai a0, a0, 31 -; LMULMAX1-NEXT: ret +; LMULMAX1-RV32-LABEL: vreduce_umax_v1i1: +; LMULMAX1-RV32: # %bb.0: +; LMULMAX1-RV32-NEXT: vsetvli a0, zero, e8, mf8, ta, ma +; LMULMAX1-RV32-NEXT: vmv.v.i v8, 0 +; LMULMAX1-RV32-NEXT: vmerge.vim v8, v8, 1, v0 +; LMULMAX1-RV32-NEXT: vmv.x.s a0, v8 +; LMULMAX1-RV32-NEXT: slli a0, a0, 31 +; LMULMAX1-RV32-NEXT: srai a0, a0, 31 +; LMULMAX1-RV32-NEXT: ret ; -; LMULMAX8-LABEL: vreduce_umax_v1i1: -; LMULMAX8: # %bb.0: -; LMULMAX8-NEXT: vsetvli a0, zero, e8, mf8, ta, ma -; LMULMAX8-NEXT: vmv.v.i v8, 0 -; LMULMAX8-NEXT: vmerge.vim v8, v8, 1, v0 -; LMULMAX8-NEXT: vmv.x.s a0, v8 -; LMULMAX8-NEXT: slli a0, a0, 63 -; LMULMAX8-NEXT: srai a0, a0, 63 -; LMULMAX8-NEXT: ret +; LMULMAX1-RV64-LABEL: vreduce_umax_v1i1: +; LMULMAX1-RV64: # %bb.0: +; LMULMAX1-RV64-NEXT: vsetvli a0, zero, e8, mf8, ta, ma +; LMULMAX1-RV64-NEXT: vmv.v.i v8, 0 +; LMULMAX1-RV64-NEXT: vmerge.vim v8, v8, 1, v0 +; LMULMAX1-RV64-NEXT: vmv.x.s a0, v8 +; LMULMAX1-RV64-NEXT: slli a0, a0, 63 +; LMULMAX1-RV64-NEXT: srai a0, a0, 63 +; LMULMAX1-RV64-NEXT: ret +; +; LMULMAX8-RV32-LABEL: vreduce_umax_v1i1: +; LMULMAX8-RV32: # %bb.0: +; LMULMAX8-RV32-NEXT: vsetvli a0, zero, e8, mf8, ta, ma +; LMULMAX8-RV32-NEXT: vmv.v.i v8, 0 +; LMULMAX8-RV32-NEXT: vmerge.vim v8, v8, 1, v0 +; LMULMAX8-RV32-NEXT: vmv.x.s a0, v8 +; LMULMAX8-RV32-NEXT: slli a0, a0, 31 +; LMULMAX8-RV32-NEXT: srai a0, a0, 31 +; LMULMAX8-RV32-NEXT: ret +; +; LMULMAX8-RV64-LABEL: vreduce_umax_v1i1: +; LMULMAX8-RV64: # %bb.0: +; LMULMAX8-RV64-NEXT: vsetvli a0, zero, e8, mf8, ta, ma +; LMULMAX8-RV64-NEXT: vmv.v.i v8, 0 +; LMULMAX8-RV64-NEXT: vmerge.vim v8, v8, 1, v0 +; LMULMAX8-RV64-NEXT: vmv.x.s a0, v8 +; LMULMAX8-RV64-NEXT: slli a0, a0, 63 +; LMULMAX8-RV64-NEXT: srai a0, a0, 63 +; LMULMAX8-RV64-NEXT: ret %red = call i1 @llvm.vector.reduce.umax.v1i1(<1 x i1> %v) ret i1 %red } @@ -111,25 +191,45 @@ define signext i1 @vreduce_umax_v1i1(<1 x i1> %v) { declare i1 @llvm.vector.reduce.smax.v1i1(<1 x i1>) define signext i1 @vreduce_smax_v1i1(<1 x i1> %v) { -; LMULMAX1-LABEL: vreduce_smax_v1i1: -; LMULMAX1: # %bb.0: -; LMULMAX1-NEXT: vsetvli a0, zero, e8, mf8, ta, ma -; LMULMAX1-NEXT: vmv.v.i v8, 0 -; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0 -; LMULMAX1-NEXT: vmv.x.s a0, v8 -; LMULMAX1-NEXT: slli a0, a0, 31 -; LMULMAX1-NEXT: srai a0, a0, 31 -; LMULMAX1-NEXT: ret +; LMULMAX1-RV32-LABEL: vreduce_smax_v1i1: +; LMULMAX1-RV32: # %bb.0: +; LMULMAX1-RV32-NEXT: vsetvli a0, zero, e8, mf8, ta, ma +; LMULMAX1-RV32-NEXT: vmv.v.i v8, 0 +; LMULMAX1-RV32-NEXT: vmerge.vim v8, v8, 1, v0 +; LMULMAX1-RV32-NEXT: vmv.x.s a0, v8 +; LMULMAX1-RV32-NEXT: slli a0, a0, 31 +; LMULMAX1-RV32-NEXT: srai a0, a0, 31 +; LMULMAX1-RV32-NEXT: ret ; -; LMULMAX8-LABEL: vreduce_smax_v1i1: -; LMULMAX8: # %bb.0: -; LMULMAX8-NEXT: vsetvli a0, zero, e8, mf8, ta, ma -; LMULMAX8-NEXT: vmv.v.i v8, 0 -; LMULMAX8-NEXT: vmerge.vim v8, v8, 1, v0 -; LMULMAX8-NEXT: vmv.x.s a0, v8 -; LMULMAX8-NEXT: slli a0, a0, 63 -; LMULMAX8-NEXT: srai a0, a0, 63 -; LMULMAX8-NEXT: ret +; LMULMAX1-RV64-LABEL: vreduce_smax_v1i1: +; LMULMAX1-RV64: # %bb.0: +; LMULMAX1-RV64-NEXT: vsetvli a0, zero, e8, mf8, ta, ma +; LMULMAX1-RV64-NEXT: vmv.v.i v8, 0 +; LMULMAX1-RV64-NEXT: vmerge.vim v8, v8, 1, v0 +; LMULMAX1-RV64-NEXT: vmv.x.s a0, v8 +; LMULMAX1-RV64-NEXT: slli a0, a0, 63 +; LMULMAX1-RV64-NEXT: srai a0, a0, 63 +; LMULMAX1-RV64-NEXT: ret +; +; LMULMAX8-RV32-LABEL: vreduce_smax_v1i1: +; LMULMAX8-RV32: # %bb.0: +; LMULMAX8-RV32-NEXT: vsetvli a0, zero, e8, mf8, ta, ma +; LMULMAX8-RV32-NEXT: vmv.v.i v8, 0 +; LMULMAX8-RV32-NEXT: vmerge.vim v8, v8, 1, v0 +; LMULMAX8-RV32-NEXT: vmv.x.s a0, v8 +; LMULMAX8-RV32-NEXT: slli a0, a0, 31 +; LMULMAX8-RV32-NEXT: srai a0, a0, 31 +; LMULMAX8-RV32-NEXT: ret +; +; LMULMAX8-RV64-LABEL: vreduce_smax_v1i1: +; LMULMAX8-RV64: # %bb.0: +; LMULMAX8-RV64-NEXT: vsetvli a0, zero, e8, mf8, ta, ma +; LMULMAX8-RV64-NEXT: vmv.v.i v8, 0 +; LMULMAX8-RV64-NEXT: vmerge.vim v8, v8, 1, v0 +; LMULMAX8-RV64-NEXT: vmv.x.s a0, v8 +; LMULMAX8-RV64-NEXT: slli a0, a0, 63 +; LMULMAX8-RV64-NEXT: srai a0, a0, 63 +; LMULMAX8-RV64-NEXT: ret %red = call i1 @llvm.vector.reduce.smax.v1i1(<1 x i1> %v) ret i1 %red } @@ -137,25 +237,45 @@ define signext i1 @vreduce_smax_v1i1(<1 x i1> %v) { declare i1 @llvm.vector.reduce.umin.v1i1(<1 x i1>) define signext i1 @vreduce_umin_v1i1(<1 x i1> %v) { -; LMULMAX1-LABEL: vreduce_umin_v1i1: -; LMULMAX1: # %bb.0: -; LMULMAX1-NEXT: vsetvli a0, zero, e8, mf8, ta, ma -; LMULMAX1-NEXT: vmv.v.i v8, 0 -; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0 -; LMULMAX1-NEXT: vmv.x.s a0, v8 -; LMULMAX1-NEXT: slli a0, a0, 31 -; LMULMAX1-NEXT: srai a0, a0, 31 -; LMULMAX1-NEXT: ret +; LMULMAX1-RV32-LABEL: vreduce_umin_v1i1: +; LMULMAX1-RV32: # %bb.0: +; LMULMAX1-RV32-NEXT: vsetvli a0, zero, e8, mf8, ta, ma +; LMULMAX1-RV32-NEXT: vmv.v.i v8, 0 +; LMULMAX1-RV32-NEXT: vmerge.vim v8, v8, 1, v0 +; LMULMAX1-RV32-NEXT: vmv.x.s a0, v8 +; LMULMAX1-RV32-NEXT: slli a0, a0, 31 +; LMULMAX1-RV32-NEXT: srai a0, a0, 31 +; LMULMAX1-RV32-NEXT: ret ; -; LMULMAX8-LABEL: vreduce_umin_v1i1: -; LMULMAX8: # %bb.0: -; LMULMAX8-NEXT: vsetvli a0, zero, e8, mf8, ta, ma -; LMULMAX8-NEXT: vmv.v.i v8, 0 -; LMULMAX8-NEXT: vmerge.vim v8, v8, 1, v0 -; LMULMAX8-NEXT: vmv.x.s a0, v8 -; LMULMAX8-NEXT: slli a0, a0, 63 -; LMULMAX8-NEXT: srai a0, a0, 63 -; LMULMAX8-NEXT: ret +; LMULMAX1-RV64-LABEL: vreduce_umin_v1i1: +; LMULMAX1-RV64: # %bb.0: +; LMULMAX1-RV64-NEXT: vsetvli a0, zero, e8, mf8, ta, ma +; LMULMAX1-RV64-NEXT: vmv.v.i v8, 0 +; LMULMAX1-RV64-NEXT: vmerge.vim v8, v8, 1, v0 +; LMULMAX1-RV64-NEXT: vmv.x.s a0, v8 +; LMULMAX1-RV64-NEXT: slli a0, a0, 63 +; LMULMAX1-RV64-NEXT: srai a0, a0, 63 +; LMULMAX1-RV64-NEXT: ret +; +; LMULMAX8-RV32-LABEL: vreduce_umin_v1i1: +; LMULMAX8-RV32: # %bb.0: +; LMULMAX8-RV32-NEXT: vsetvli a0, zero, e8, mf8, ta, ma +; LMULMAX8-RV32-NEXT: vmv.v.i v8, 0 +; LMULMAX8-RV32-NEXT: vmerge.vim v8, v8, 1, v0 +; LMULMAX8-RV32-NEXT: vmv.x.s a0, v8 +; LMULMAX8-RV32-NEXT: slli a0, a0, 31 +; LMULMAX8-RV32-NEXT: srai a0, a0, 31 +; LMULMAX8-RV32-NEXT: ret +; +; LMULMAX8-RV64-LABEL: vreduce_umin_v1i1: +; LMULMAX8-RV64: # %bb.0: +; LMULMAX8-RV64-NEXT: vsetvli a0, zero, e8, mf8, ta, ma +; LMULMAX8-RV64-NEXT: vmv.v.i v8, 0 +; LMULMAX8-RV64-NEXT: vmerge.vim v8, v8, 1, v0 +; LMULMAX8-RV64-NEXT: vmv.x.s a0, v8 +; LMULMAX8-RV64-NEXT: slli a0, a0, 63 +; LMULMAX8-RV64-NEXT: srai a0, a0, 63 +; LMULMAX8-RV64-NEXT: ret %red = call i1 @llvm.vector.reduce.umin.v1i1(<1 x i1> %v) ret i1 %red } @@ -163,25 +283,45 @@ define signext i1 @vreduce_umin_v1i1(<1 x i1> %v) { declare i1 @llvm.vector.reduce.smin.v1i1(<1 x i1>) define signext i1 @vreduce_smin_v1i1(<1 x i1> %v) { -; LMULMAX1-LABEL: vreduce_smin_v1i1: -; LMULMAX1: # %bb.0: -; LMULMAX1-NEXT: vsetvli a0, zero, e8, mf8, ta, ma -; LMULMAX1-NEXT: vmv.v.i v8, 0 -; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0 -; LMULMAX1-NEXT: vmv.x.s a0, v8 -; LMULMAX1-NEXT: slli a0, a0, 31 -; LMULMAX1-NEXT: srai a0, a0, 31 -; LMULMAX1-NEXT: ret +; LMULMAX1-RV32-LABEL: vreduce_smin_v1i1: +; LMULMAX1-RV32: # %bb.0: +; LMULMAX1-RV32-NEXT: vsetvli a0, zero, e8, mf8, ta, ma +; LMULMAX1-RV32-NEXT: vmv.v.i v8, 0 +; LMULMAX1-RV32-NEXT: vmerge.vim v8, v8, 1, v0 +; LMULMAX1-RV32-NEXT: vmv.x.s a0, v8 +; LMULMAX1-RV32-NEXT: slli a0, a0, 31 +; LMULMAX1-RV32-NEXT: srai a0, a0, 31 +; LMULMAX1-RV32-NEXT: ret ; -; LMULMAX8-LABEL: vreduce_smin_v1i1: -; LMULMAX8: # %bb.0: -; LMULMAX8-NEXT: vsetvli a0, zero, e8, mf8, ta, ma -; LMULMAX8-NEXT: vmv.v.i v8, 0 -; LMULMAX8-NEXT: vmerge.vim v8, v8, 1, v0 -; LMULMAX8-NEXT: vmv.x.s a0, v8 -; LMULMAX8-NEXT: slli a0, a0, 63 -; LMULMAX8-NEXT: srai a0, a0, 63 -; LMULMAX8-NEXT: ret +; LMULMAX1-RV64-LABEL: vreduce_smin_v1i1: +; LMULMAX1-RV64: # %bb.0: +; LMULMAX1-RV64-NEXT: vsetvli a0, zero, e8, mf8, ta, ma +; LMULMAX1-RV64-NEXT: vmv.v.i v8, 0 +; LMULMAX1-RV64-NEXT: vmerge.vim v8, v8, 1, v0 +; LMULMAX1-RV64-NEXT: vmv.x.s a0, v8 +; LMULMAX1-RV64-NEXT: slli a0, a0, 63 +; LMULMAX1-RV64-NEXT: srai a0, a0, 63 +; LMULMAX1-RV64-NEXT: ret +; +; LMULMAX8-RV32-LABEL: vreduce_smin_v1i1: +; LMULMAX8-RV32: # %bb.0: +; LMULMAX8-RV32-NEXT: vsetvli a0, zero, e8, mf8, ta, ma +; LMULMAX8-RV32-NEXT: vmv.v.i v8, 0 +; LMULMAX8-RV32-NEXT: vmerge.vim v8, v8, 1, v0 +; LMULMAX8-RV32-NEXT: vmv.x.s a0, v8 +; LMULMAX8-RV32-NEXT: slli a0, a0, 31 +; LMULMAX8-RV32-NEXT: srai a0, a0, 31 +; LMULMAX8-RV32-NEXT: ret +; +; LMULMAX8-RV64-LABEL: vreduce_smin_v1i1: +; LMULMAX8-RV64: # %bb.0: +; LMULMAX8-RV64-NEXT: vsetvli a0, zero, e8, mf8, ta, ma +; LMULMAX8-RV64-NEXT: vmv.v.i v8, 0 +; LMULMAX8-RV64-NEXT: vmerge.vim v8, v8, 1, v0 +; LMULMAX8-RV64-NEXT: vmv.x.s a0, v8 +; LMULMAX8-RV64-NEXT: slli a0, a0, 63 +; LMULMAX8-RV64-NEXT: srai a0, a0, 63 +; LMULMAX8-RV64-NEXT: ret %red = call i1 @llvm.vector.reduce.smin.v1i1(<1 x i1> %v) ret i1 %red } @@ -203,21 +343,37 @@ define signext i1 @vreduce_or_v2i1(<2 x i1> %v) { declare i1 @llvm.vector.reduce.xor.v2i1(<2 x i1>) define signext i1 @vreduce_xor_v2i1(<2 x i1> %v) { -; LMULMAX1-LABEL: vreduce_xor_v2i1: -; LMULMAX1: # %bb.0: -; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf8, ta, ma -; LMULMAX1-NEXT: vcpop.m a0, v0 -; LMULMAX1-NEXT: slli a0, a0, 31 -; LMULMAX1-NEXT: srai a0, a0, 31 -; LMULMAX1-NEXT: ret +; LMULMAX1-RV32-LABEL: vreduce_xor_v2i1: +; LMULMAX1-RV32: # %bb.0: +; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, ma +; LMULMAX1-RV32-NEXT: vcpop.m a0, v0 +; LMULMAX1-RV32-NEXT: slli a0, a0, 31 +; LMULMAX1-RV32-NEXT: srai a0, a0, 31 +; LMULMAX1-RV32-NEXT: ret ; -; LMULMAX8-LABEL: vreduce_xor_v2i1: -; LMULMAX8: # %bb.0: -; LMULMAX8-NEXT: vsetivli zero, 2, e8, mf8, ta, ma -; LMULMAX8-NEXT: vcpop.m a0, v0 -; LMULMAX8-NEXT: slli a0, a0, 63 -; LMULMAX8-NEXT: srai a0, a0, 63 -; LMULMAX8-NEXT: ret +; LMULMAX1-RV64-LABEL: vreduce_xor_v2i1: +; LMULMAX1-RV64: # %bb.0: +; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, ma +; LMULMAX1-RV64-NEXT: vcpop.m a0, v0 +; LMULMAX1-RV64-NEXT: slli a0, a0, 63 +; LMULMAX1-RV64-NEXT: srai a0, a0, 63 +; LMULMAX1-RV64-NEXT: ret +; +; LMULMAX8-RV32-LABEL: vreduce_xor_v2i1: +; LMULMAX8-RV32: # %bb.0: +; LMULMAX8-RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, ma +; LMULMAX8-RV32-NEXT: vcpop.m a0, v0 +; LMULMAX8-RV32-NEXT: slli a0, a0, 31 +; LMULMAX8-RV32-NEXT: srai a0, a0, 31 +; LMULMAX8-RV32-NEXT: ret +; +; LMULMAX8-RV64-LABEL: vreduce_xor_v2i1: +; LMULMAX8-RV64: # %bb.0: +; LMULMAX8-RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, ma +; LMULMAX8-RV64-NEXT: vcpop.m a0, v0 +; LMULMAX8-RV64-NEXT: slli a0, a0, 63 +; LMULMAX8-RV64-NEXT: srai a0, a0, 63 +; LMULMAX8-RV64-NEXT: ret %red = call i1 @llvm.vector.reduce.xor.v2i1(<2 x i1> %v) ret i1 %red } @@ -312,21 +468,37 @@ define signext i1 @vreduce_or_v4i1(<4 x i1> %v) { declare i1 @llvm.vector.reduce.xor.v4i1(<4 x i1>) define signext i1 @vreduce_xor_v4i1(<4 x i1> %v) { -; LMULMAX1-LABEL: vreduce_xor_v4i1: -; LMULMAX1: # %bb.0: -; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf4, ta, ma -; LMULMAX1-NEXT: vcpop.m a0, v0 -; LMULMAX1-NEXT: slli a0, a0, 31 -; LMULMAX1-NEXT: srai a0, a0, 31 -; LMULMAX1-NEXT: ret +; LMULMAX1-RV32-LABEL: vreduce_xor_v4i1: +; LMULMAX1-RV32: # %bb.0: +; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, ma +; LMULMAX1-RV32-NEXT: vcpop.m a0, v0 +; LMULMAX1-RV32-NEXT: slli a0, a0, 31 +; LMULMAX1-RV32-NEXT: srai a0, a0, 31 +; LMULMAX1-RV32-NEXT: ret ; -; LMULMAX8-LABEL: vreduce_xor_v4i1: -; LMULMAX8: # %bb.0: -; LMULMAX8-NEXT: vsetivli zero, 4, e8, mf4, ta, ma -; LMULMAX8-NEXT: vcpop.m a0, v0 -; LMULMAX8-NEXT: slli a0, a0, 63 -; LMULMAX8-NEXT: srai a0, a0, 63 -; LMULMAX8-NEXT: ret +; LMULMAX1-RV64-LABEL: vreduce_xor_v4i1: +; LMULMAX1-RV64: # %bb.0: +; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, ma +; LMULMAX1-RV64-NEXT: vcpop.m a0, v0 +; LMULMAX1-RV64-NEXT: slli a0, a0, 63 +; LMULMAX1-RV64-NEXT: srai a0, a0, 63 +; LMULMAX1-RV64-NEXT: ret +; +; LMULMAX8-RV32-LABEL: vreduce_xor_v4i1: +; LMULMAX8-RV32: # %bb.0: +; LMULMAX8-RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, ma +; LMULMAX8-RV32-NEXT: vcpop.m a0, v0 +; LMULMAX8-RV32-NEXT: slli a0, a0, 31 +; LMULMAX8-RV32-NEXT: srai a0, a0, 31 +; LMULMAX8-RV32-NEXT: ret +; +; LMULMAX8-RV64-LABEL: vreduce_xor_v4i1: +; LMULMAX8-RV64: # %bb.0: +; LMULMAX8-RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, ma +; LMULMAX8-RV64-NEXT: vcpop.m a0, v0 +; LMULMAX8-RV64-NEXT: slli a0, a0, 63 +; LMULMAX8-RV64-NEXT: srai a0, a0, 63 +; LMULMAX8-RV64-NEXT: ret %red = call i1 @llvm.vector.reduce.xor.v4i1(<4 x i1> %v) ret i1 %red } @@ -421,21 +593,37 @@ define signext i1 @vreduce_or_v8i1(<8 x i1> %v) { declare i1 @llvm.vector.reduce.xor.v8i1(<8 x i1>) define signext i1 @vreduce_xor_v8i1(<8 x i1> %v) { -; LMULMAX1-LABEL: vreduce_xor_v8i1: -; LMULMAX1: # %bb.0: -; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, ma -; LMULMAX1-NEXT: vcpop.m a0, v0 -; LMULMAX1-NEXT: slli a0, a0, 31 -; LMULMAX1-NEXT: srai a0, a0, 31 -; LMULMAX1-NEXT: ret +; LMULMAX1-RV32-LABEL: vreduce_xor_v8i1: +; LMULMAX1-RV32: # %bb.0: +; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; LMULMAX1-RV32-NEXT: vcpop.m a0, v0 +; LMULMAX1-RV32-NEXT: slli a0, a0, 31 +; LMULMAX1-RV32-NEXT: srai a0, a0, 31 +; LMULMAX1-RV32-NEXT: ret ; -; LMULMAX8-LABEL: vreduce_xor_v8i1: -; LMULMAX8: # %bb.0: -; LMULMAX8-NEXT: vsetivli zero, 8, e8, mf2, ta, ma -; LMULMAX8-NEXT: vcpop.m a0, v0 -; LMULMAX8-NEXT: slli a0, a0, 63 -; LMULMAX8-NEXT: srai a0, a0, 63 -; LMULMAX8-NEXT: ret +; LMULMAX1-RV64-LABEL: vreduce_xor_v8i1: +; LMULMAX1-RV64: # %bb.0: +; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; LMULMAX1-RV64-NEXT: vcpop.m a0, v0 +; LMULMAX1-RV64-NEXT: slli a0, a0, 63 +; LMULMAX1-RV64-NEXT: srai a0, a0, 63 +; LMULMAX1-RV64-NEXT: ret +; +; LMULMAX8-RV32-LABEL: vreduce_xor_v8i1: +; LMULMAX8-RV32: # %bb.0: +; LMULMAX8-RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; LMULMAX8-RV32-NEXT: vcpop.m a0, v0 +; LMULMAX8-RV32-NEXT: slli a0, a0, 31 +; LMULMAX8-RV32-NEXT: srai a0, a0, 31 +; LMULMAX8-RV32-NEXT: ret +; +; LMULMAX8-RV64-LABEL: vreduce_xor_v8i1: +; LMULMAX8-RV64: # %bb.0: +; LMULMAX8-RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; LMULMAX8-RV64-NEXT: vcpop.m a0, v0 +; LMULMAX8-RV64-NEXT: slli a0, a0, 63 +; LMULMAX8-RV64-NEXT: srai a0, a0, 63 +; LMULMAX8-RV64-NEXT: ret %red = call i1 @llvm.vector.reduce.xor.v8i1(<8 x i1> %v) ret i1 %red } @@ -530,21 +718,37 @@ define signext i1 @vreduce_or_v16i1(<16 x i1> %v) { declare i1 @llvm.vector.reduce.xor.v16i1(<16 x i1>) define signext i1 @vreduce_xor_v16i1(<16 x i1> %v) { -; LMULMAX1-LABEL: vreduce_xor_v16i1: -; LMULMAX1: # %bb.0: -; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma -; LMULMAX1-NEXT: vcpop.m a0, v0 -; LMULMAX1-NEXT: slli a0, a0, 31 -; LMULMAX1-NEXT: srai a0, a0, 31 -; LMULMAX1-NEXT: ret +; LMULMAX1-RV32-LABEL: vreduce_xor_v16i1: +; LMULMAX1-RV32: # %bb.0: +; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; LMULMAX1-RV32-NEXT: vcpop.m a0, v0 +; LMULMAX1-RV32-NEXT: slli a0, a0, 31 +; LMULMAX1-RV32-NEXT: srai a0, a0, 31 +; LMULMAX1-RV32-NEXT: ret ; -; LMULMAX8-LABEL: vreduce_xor_v16i1: -; LMULMAX8: # %bb.0: -; LMULMAX8-NEXT: vsetivli zero, 16, e8, m1, ta, ma -; LMULMAX8-NEXT: vcpop.m a0, v0 -; LMULMAX8-NEXT: slli a0, a0, 63 -; LMULMAX8-NEXT: srai a0, a0, 63 -; LMULMAX8-NEXT: ret +; LMULMAX1-RV64-LABEL: vreduce_xor_v16i1: +; LMULMAX1-RV64: # %bb.0: +; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; LMULMAX1-RV64-NEXT: vcpop.m a0, v0 +; LMULMAX1-RV64-NEXT: slli a0, a0, 63 +; LMULMAX1-RV64-NEXT: srai a0, a0, 63 +; LMULMAX1-RV64-NEXT: ret +; +; LMULMAX8-RV32-LABEL: vreduce_xor_v16i1: +; LMULMAX8-RV32: # %bb.0: +; LMULMAX8-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; LMULMAX8-RV32-NEXT: vcpop.m a0, v0 +; LMULMAX8-RV32-NEXT: slli a0, a0, 31 +; LMULMAX8-RV32-NEXT: srai a0, a0, 31 +; LMULMAX8-RV32-NEXT: ret +; +; LMULMAX8-RV64-LABEL: vreduce_xor_v16i1: +; LMULMAX8-RV64: # %bb.0: +; LMULMAX8-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; LMULMAX8-RV64-NEXT: vcpop.m a0, v0 +; LMULMAX8-RV64-NEXT: slli a0, a0, 63 +; LMULMAX8-RV64-NEXT: srai a0, a0, 63 +; LMULMAX8-RV64-NEXT: ret %red = call i1 @llvm.vector.reduce.xor.v16i1(<16 x i1> %v) ret i1 %red } @@ -649,23 +853,41 @@ define signext i1 @vreduce_or_v32i1(<32 x i1> %v) { declare i1 @llvm.vector.reduce.xor.v32i1(<32 x i1>) define signext i1 @vreduce_xor_v32i1(<32 x i1> %v) { -; LMULMAX1-LABEL: vreduce_xor_v32i1: -; LMULMAX1: # %bb.0: -; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma -; LMULMAX1-NEXT: vmxor.mm v8, v0, v8 -; LMULMAX1-NEXT: vcpop.m a0, v8 -; LMULMAX1-NEXT: slli a0, a0, 31 -; LMULMAX1-NEXT: srai a0, a0, 31 -; LMULMAX1-NEXT: ret +; LMULMAX1-RV32-LABEL: vreduce_xor_v32i1: +; LMULMAX1-RV32: # %bb.0: +; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; LMULMAX1-RV32-NEXT: vmxor.mm v8, v0, v8 +; LMULMAX1-RV32-NEXT: vcpop.m a0, v8 +; LMULMAX1-RV32-NEXT: slli a0, a0, 31 +; LMULMAX1-RV32-NEXT: srai a0, a0, 31 +; LMULMAX1-RV32-NEXT: ret ; -; LMULMAX8-LABEL: vreduce_xor_v32i1: -; LMULMAX8: # %bb.0: -; LMULMAX8-NEXT: li a0, 32 -; LMULMAX8-NEXT: vsetvli zero, a0, e8, m2, ta, ma -; LMULMAX8-NEXT: vcpop.m a0, v0 -; LMULMAX8-NEXT: slli a0, a0, 63 -; LMULMAX8-NEXT: srai a0, a0, 63 -; LMULMAX8-NEXT: ret +; LMULMAX1-RV64-LABEL: vreduce_xor_v32i1: +; LMULMAX1-RV64: # %bb.0: +; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; LMULMAX1-RV64-NEXT: vmxor.mm v8, v0, v8 +; LMULMAX1-RV64-NEXT: vcpop.m a0, v8 +; LMULMAX1-RV64-NEXT: slli a0, a0, 63 +; LMULMAX1-RV64-NEXT: srai a0, a0, 63 +; LMULMAX1-RV64-NEXT: ret +; +; LMULMAX8-RV32-LABEL: vreduce_xor_v32i1: +; LMULMAX8-RV32: # %bb.0: +; LMULMAX8-RV32-NEXT: li a0, 32 +; LMULMAX8-RV32-NEXT: vsetvli zero, a0, e8, m2, ta, ma +; LMULMAX8-RV32-NEXT: vcpop.m a0, v0 +; LMULMAX8-RV32-NEXT: slli a0, a0, 31 +; LMULMAX8-RV32-NEXT: srai a0, a0, 31 +; LMULMAX8-RV32-NEXT: ret +; +; LMULMAX8-RV64-LABEL: vreduce_xor_v32i1: +; LMULMAX8-RV64: # %bb.0: +; LMULMAX8-RV64-NEXT: li a0, 32 +; LMULMAX8-RV64-NEXT: vsetvli zero, a0, e8, m2, ta, ma +; LMULMAX8-RV64-NEXT: vcpop.m a0, v0 +; LMULMAX8-RV64-NEXT: slli a0, a0, 63 +; LMULMAX8-RV64-NEXT: srai a0, a0, 63 +; LMULMAX8-RV64-NEXT: ret %red = call i1 @llvm.vector.reduce.xor.v32i1(<32 x i1> %v) ret i1 %red } @@ -822,25 +1044,45 @@ define signext i1 @vreduce_or_v64i1(<64 x i1> %v) { declare i1 @llvm.vector.reduce.xor.v64i1(<64 x i1>) define signext i1 @vreduce_xor_v64i1(<64 x i1> %v) { -; LMULMAX1-LABEL: vreduce_xor_v64i1: -; LMULMAX1: # %bb.0: -; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma -; LMULMAX1-NEXT: vmxor.mm v8, v8, v10 -; LMULMAX1-NEXT: vmxor.mm v9, v0, v9 -; LMULMAX1-NEXT: vmxor.mm v8, v9, v8 -; LMULMAX1-NEXT: vcpop.m a0, v8 -; LMULMAX1-NEXT: slli a0, a0, 31 -; LMULMAX1-NEXT: srai a0, a0, 31 -; LMULMAX1-NEXT: ret +; LMULMAX1-RV32-LABEL: vreduce_xor_v64i1: +; LMULMAX1-RV32: # %bb.0: +; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; LMULMAX1-RV32-NEXT: vmxor.mm v8, v8, v10 +; LMULMAX1-RV32-NEXT: vmxor.mm v9, v0, v9 +; LMULMAX1-RV32-NEXT: vmxor.mm v8, v9, v8 +; LMULMAX1-RV32-NEXT: vcpop.m a0, v8 +; LMULMAX1-RV32-NEXT: slli a0, a0, 31 +; LMULMAX1-RV32-NEXT: srai a0, a0, 31 +; LMULMAX1-RV32-NEXT: ret ; -; LMULMAX8-LABEL: vreduce_xor_v64i1: -; LMULMAX8: # %bb.0: -; LMULMAX8-NEXT: li a0, 64 -; LMULMAX8-NEXT: vsetvli zero, a0, e8, m4, ta, ma -; LMULMAX8-NEXT: vcpop.m a0, v0 -; LMULMAX8-NEXT: slli a0, a0, 63 -; LMULMAX8-NEXT: srai a0, a0, 63 -; LMULMAX8-NEXT: ret +; LMULMAX1-RV64-LABEL: vreduce_xor_v64i1: +; LMULMAX1-RV64: # %bb.0: +; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; LMULMAX1-RV64-NEXT: vmxor.mm v8, v8, v10 +; LMULMAX1-RV64-NEXT: vmxor.mm v9, v0, v9 +; LMULMAX1-RV64-NEXT: vmxor.mm v8, v9, v8 +; LMULMAX1-RV64-NEXT: vcpop.m a0, v8 +; LMULMAX1-RV64-NEXT: slli a0, a0, 63 +; LMULMAX1-RV64-NEXT: srai a0, a0, 63 +; LMULMAX1-RV64-NEXT: ret +; +; LMULMAX8-RV32-LABEL: vreduce_xor_v64i1: +; LMULMAX8-RV32: # %bb.0: +; LMULMAX8-RV32-NEXT: li a0, 64 +; LMULMAX8-RV32-NEXT: vsetvli zero, a0, e8, m4, ta, ma +; LMULMAX8-RV32-NEXT: vcpop.m a0, v0 +; LMULMAX8-RV32-NEXT: slli a0, a0, 31 +; LMULMAX8-RV32-NEXT: srai a0, a0, 31 +; LMULMAX8-RV32-NEXT: ret +; +; LMULMAX8-RV64-LABEL: vreduce_xor_v64i1: +; LMULMAX8-RV64: # %bb.0: +; LMULMAX8-RV64-NEXT: li a0, 64 +; LMULMAX8-RV64-NEXT: vsetvli zero, a0, e8, m4, ta, ma +; LMULMAX8-RV64-NEXT: vcpop.m a0, v0 +; LMULMAX8-RV64-NEXT: slli a0, a0, 63 +; LMULMAX8-RV64-NEXT: srai a0, a0, 63 +; LMULMAX8-RV64-NEXT: ret %red = call i1 @llvm.vector.reduce.xor.v64i1(<64 x i1> %v) ret i1 %red } @@ -981,25 +1223,45 @@ define signext i1 @vreduce_smin_v64i1(<64 x i1> %v) { declare i1 @llvm.vector.reduce.add.v1i1(<1 x i1>) define signext i1 @vreduce_add_v1i1(<1 x i1> %v) { -; LMULMAX1-LABEL: vreduce_add_v1i1: -; LMULMAX1: # %bb.0: -; LMULMAX1-NEXT: vsetvli a0, zero, e8, mf8, ta, ma -; LMULMAX1-NEXT: vmv.v.i v8, 0 -; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0 -; LMULMAX1-NEXT: vmv.x.s a0, v8 -; LMULMAX1-NEXT: slli a0, a0, 31 -; LMULMAX1-NEXT: srai a0, a0, 31 -; LMULMAX1-NEXT: ret +; LMULMAX1-RV32-LABEL: vreduce_add_v1i1: +; LMULMAX1-RV32: # %bb.0: +; LMULMAX1-RV32-NEXT: vsetvli a0, zero, e8, mf8, ta, ma +; LMULMAX1-RV32-NEXT: vmv.v.i v8, 0 +; LMULMAX1-RV32-NEXT: vmerge.vim v8, v8, 1, v0 +; LMULMAX1-RV32-NEXT: vmv.x.s a0, v8 +; LMULMAX1-RV32-NEXT: slli a0, a0, 31 +; LMULMAX1-RV32-NEXT: srai a0, a0, 31 +; LMULMAX1-RV32-NEXT: ret ; -; LMULMAX8-LABEL: vreduce_add_v1i1: -; LMULMAX8: # %bb.0: -; LMULMAX8-NEXT: vsetvli a0, zero, e8, mf8, ta, ma -; LMULMAX8-NEXT: vmv.v.i v8, 0 -; LMULMAX8-NEXT: vmerge.vim v8, v8, 1, v0 -; LMULMAX8-NEXT: vmv.x.s a0, v8 -; LMULMAX8-NEXT: slli a0, a0, 63 -; LMULMAX8-NEXT: srai a0, a0, 63 -; LMULMAX8-NEXT: ret +; LMULMAX1-RV64-LABEL: vreduce_add_v1i1: +; LMULMAX1-RV64: # %bb.0: +; LMULMAX1-RV64-NEXT: vsetvli a0, zero, e8, mf8, ta, ma +; LMULMAX1-RV64-NEXT: vmv.v.i v8, 0 +; LMULMAX1-RV64-NEXT: vmerge.vim v8, v8, 1, v0 +; LMULMAX1-RV64-NEXT: vmv.x.s a0, v8 +; LMULMAX1-RV64-NEXT: slli a0, a0, 63 +; LMULMAX1-RV64-NEXT: srai a0, a0, 63 +; LMULMAX1-RV64-NEXT: ret +; +; LMULMAX8-RV32-LABEL: vreduce_add_v1i1: +; LMULMAX8-RV32: # %bb.0: +; LMULMAX8-RV32-NEXT: vsetvli a0, zero, e8, mf8, ta, ma +; LMULMAX8-RV32-NEXT: vmv.v.i v8, 0 +; LMULMAX8-RV32-NEXT: vmerge.vim v8, v8, 1, v0 +; LMULMAX8-RV32-NEXT: vmv.x.s a0, v8 +; LMULMAX8-RV32-NEXT: slli a0, a0, 31 +; LMULMAX8-RV32-NEXT: srai a0, a0, 31 +; LMULMAX8-RV32-NEXT: ret +; +; LMULMAX8-RV64-LABEL: vreduce_add_v1i1: +; LMULMAX8-RV64: # %bb.0: +; LMULMAX8-RV64-NEXT: vsetvli a0, zero, e8, mf8, ta, ma +; LMULMAX8-RV64-NEXT: vmv.v.i v8, 0 +; LMULMAX8-RV64-NEXT: vmerge.vim v8, v8, 1, v0 +; LMULMAX8-RV64-NEXT: vmv.x.s a0, v8 +; LMULMAX8-RV64-NEXT: slli a0, a0, 63 +; LMULMAX8-RV64-NEXT: srai a0, a0, 63 +; LMULMAX8-RV64-NEXT: ret %red = call i1 @llvm.vector.reduce.add.v1i1(<1 x i1> %v) ret i1 %red } @@ -1007,21 +1269,37 @@ define signext i1 @vreduce_add_v1i1(<1 x i1> %v) { declare i1 @llvm.vector.reduce.add.v2i1(<2 x i1>) define signext i1 @vreduce_add_v2i1(<2 x i1> %v) { -; LMULMAX1-LABEL: vreduce_add_v2i1: -; LMULMAX1: # %bb.0: -; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf8, ta, ma -; LMULMAX1-NEXT: vcpop.m a0, v0 -; LMULMAX1-NEXT: slli a0, a0, 31 -; LMULMAX1-NEXT: srai a0, a0, 31 -; LMULMAX1-NEXT: ret +; LMULMAX1-RV32-LABEL: vreduce_add_v2i1: +; LMULMAX1-RV32: # %bb.0: +; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, ma +; LMULMAX1-RV32-NEXT: vcpop.m a0, v0 +; LMULMAX1-RV32-NEXT: slli a0, a0, 31 +; LMULMAX1-RV32-NEXT: srai a0, a0, 31 +; LMULMAX1-RV32-NEXT: ret ; -; LMULMAX8-LABEL: vreduce_add_v2i1: -; LMULMAX8: # %bb.0: -; LMULMAX8-NEXT: vsetivli zero, 2, e8, mf8, ta, ma -; LMULMAX8-NEXT: vcpop.m a0, v0 -; LMULMAX8-NEXT: slli a0, a0, 63 -; LMULMAX8-NEXT: srai a0, a0, 63 -; LMULMAX8-NEXT: ret +; LMULMAX1-RV64-LABEL: vreduce_add_v2i1: +; LMULMAX1-RV64: # %bb.0: +; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, ma +; LMULMAX1-RV64-NEXT: vcpop.m a0, v0 +; LMULMAX1-RV64-NEXT: slli a0, a0, 63 +; LMULMAX1-RV64-NEXT: srai a0, a0, 63 +; LMULMAX1-RV64-NEXT: ret +; +; LMULMAX8-RV32-LABEL: vreduce_add_v2i1: +; LMULMAX8-RV32: # %bb.0: +; LMULMAX8-RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, ma +; LMULMAX8-RV32-NEXT: vcpop.m a0, v0 +; LMULMAX8-RV32-NEXT: slli a0, a0, 31 +; LMULMAX8-RV32-NEXT: srai a0, a0, 31 +; LMULMAX8-RV32-NEXT: ret +; +; LMULMAX8-RV64-LABEL: vreduce_add_v2i1: +; LMULMAX8-RV64: # %bb.0: +; LMULMAX8-RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, ma +; LMULMAX8-RV64-NEXT: vcpop.m a0, v0 +; LMULMAX8-RV64-NEXT: slli a0, a0, 63 +; LMULMAX8-RV64-NEXT: srai a0, a0, 63 +; LMULMAX8-RV64-NEXT: ret %red = call i1 @llvm.vector.reduce.add.v2i1(<2 x i1> %v) ret i1 %red } @@ -1029,21 +1307,37 @@ define signext i1 @vreduce_add_v2i1(<2 x i1> %v) { declare i1 @llvm.vector.reduce.add.v4i1(<4 x i1>) define signext i1 @vreduce_add_v4i1(<4 x i1> %v) { -; LMULMAX1-LABEL: vreduce_add_v4i1: -; LMULMAX1: # %bb.0: -; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf4, ta, ma -; LMULMAX1-NEXT: vcpop.m a0, v0 -; LMULMAX1-NEXT: slli a0, a0, 31 -; LMULMAX1-NEXT: srai a0, a0, 31 -; LMULMAX1-NEXT: ret +; LMULMAX1-RV32-LABEL: vreduce_add_v4i1: +; LMULMAX1-RV32: # %bb.0: +; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, ma +; LMULMAX1-RV32-NEXT: vcpop.m a0, v0 +; LMULMAX1-RV32-NEXT: slli a0, a0, 31 +; LMULMAX1-RV32-NEXT: srai a0, a0, 31 +; LMULMAX1-RV32-NEXT: ret ; -; LMULMAX8-LABEL: vreduce_add_v4i1: -; LMULMAX8: # %bb.0: -; LMULMAX8-NEXT: vsetivli zero, 4, e8, mf4, ta, ma -; LMULMAX8-NEXT: vcpop.m a0, v0 -; LMULMAX8-NEXT: slli a0, a0, 63 -; LMULMAX8-NEXT: srai a0, a0, 63 -; LMULMAX8-NEXT: ret +; LMULMAX1-RV64-LABEL: vreduce_add_v4i1: +; LMULMAX1-RV64: # %bb.0: +; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, ma +; LMULMAX1-RV64-NEXT: vcpop.m a0, v0 +; LMULMAX1-RV64-NEXT: slli a0, a0, 63 +; LMULMAX1-RV64-NEXT: srai a0, a0, 63 +; LMULMAX1-RV64-NEXT: ret +; +; LMULMAX8-RV32-LABEL: vreduce_add_v4i1: +; LMULMAX8-RV32: # %bb.0: +; LMULMAX8-RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, ma +; LMULMAX8-RV32-NEXT: vcpop.m a0, v0 +; LMULMAX8-RV32-NEXT: slli a0, a0, 31 +; LMULMAX8-RV32-NEXT: srai a0, a0, 31 +; LMULMAX8-RV32-NEXT: ret +; +; LMULMAX8-RV64-LABEL: vreduce_add_v4i1: +; LMULMAX8-RV64: # %bb.0: +; LMULMAX8-RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, ma +; LMULMAX8-RV64-NEXT: vcpop.m a0, v0 +; LMULMAX8-RV64-NEXT: slli a0, a0, 63 +; LMULMAX8-RV64-NEXT: srai a0, a0, 63 +; LMULMAX8-RV64-NEXT: ret %red = call i1 @llvm.vector.reduce.add.v4i1(<4 x i1> %v) ret i1 %red } @@ -1051,21 +1345,37 @@ define signext i1 @vreduce_add_v4i1(<4 x i1> %v) { declare i1 @llvm.vector.reduce.add.v8i1(<8 x i1>) define signext i1 @vreduce_add_v8i1(<8 x i1> %v) { -; LMULMAX1-LABEL: vreduce_add_v8i1: -; LMULMAX1: # %bb.0: -; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, ma -; LMULMAX1-NEXT: vcpop.m a0, v0 -; LMULMAX1-NEXT: slli a0, a0, 31 -; LMULMAX1-NEXT: srai a0, a0, 31 -; LMULMAX1-NEXT: ret +; LMULMAX1-RV32-LABEL: vreduce_add_v8i1: +; LMULMAX1-RV32: # %bb.0: +; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; LMULMAX1-RV32-NEXT: vcpop.m a0, v0 +; LMULMAX1-RV32-NEXT: slli a0, a0, 31 +; LMULMAX1-RV32-NEXT: srai a0, a0, 31 +; LMULMAX1-RV32-NEXT: ret ; -; LMULMAX8-LABEL: vreduce_add_v8i1: -; LMULMAX8: # %bb.0: -; LMULMAX8-NEXT: vsetivli zero, 8, e8, mf2, ta, ma -; LMULMAX8-NEXT: vcpop.m a0, v0 -; LMULMAX8-NEXT: slli a0, a0, 63 -; LMULMAX8-NEXT: srai a0, a0, 63 -; LMULMAX8-NEXT: ret +; LMULMAX1-RV64-LABEL: vreduce_add_v8i1: +; LMULMAX1-RV64: # %bb.0: +; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; LMULMAX1-RV64-NEXT: vcpop.m a0, v0 +; LMULMAX1-RV64-NEXT: slli a0, a0, 63 +; LMULMAX1-RV64-NEXT: srai a0, a0, 63 +; LMULMAX1-RV64-NEXT: ret +; +; LMULMAX8-RV32-LABEL: vreduce_add_v8i1: +; LMULMAX8-RV32: # %bb.0: +; LMULMAX8-RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; LMULMAX8-RV32-NEXT: vcpop.m a0, v0 +; LMULMAX8-RV32-NEXT: slli a0, a0, 31 +; LMULMAX8-RV32-NEXT: srai a0, a0, 31 +; LMULMAX8-RV32-NEXT: ret +; +; LMULMAX8-RV64-LABEL: vreduce_add_v8i1: +; LMULMAX8-RV64: # %bb.0: +; LMULMAX8-RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; LMULMAX8-RV64-NEXT: vcpop.m a0, v0 +; LMULMAX8-RV64-NEXT: slli a0, a0, 63 +; LMULMAX8-RV64-NEXT: srai a0, a0, 63 +; LMULMAX8-RV64-NEXT: ret %red = call i1 @llvm.vector.reduce.add.v8i1(<8 x i1> %v) ret i1 %red } @@ -1073,21 +1383,37 @@ define signext i1 @vreduce_add_v8i1(<8 x i1> %v) { declare i1 @llvm.vector.reduce.add.v16i1(<16 x i1>) define signext i1 @vreduce_add_v16i1(<16 x i1> %v) { -; LMULMAX1-LABEL: vreduce_add_v16i1: -; LMULMAX1: # %bb.0: -; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma -; LMULMAX1-NEXT: vcpop.m a0, v0 -; LMULMAX1-NEXT: slli a0, a0, 31 -; LMULMAX1-NEXT: srai a0, a0, 31 -; LMULMAX1-NEXT: ret +; LMULMAX1-RV32-LABEL: vreduce_add_v16i1: +; LMULMAX1-RV32: # %bb.0: +; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; LMULMAX1-RV32-NEXT: vcpop.m a0, v0 +; LMULMAX1-RV32-NEXT: slli a0, a0, 31 +; LMULMAX1-RV32-NEXT: srai a0, a0, 31 +; LMULMAX1-RV32-NEXT: ret ; -; LMULMAX8-LABEL: vreduce_add_v16i1: -; LMULMAX8: # %bb.0: -; LMULMAX8-NEXT: vsetivli zero, 16, e8, m1, ta, ma -; LMULMAX8-NEXT: vcpop.m a0, v0 -; LMULMAX8-NEXT: slli a0, a0, 63 -; LMULMAX8-NEXT: srai a0, a0, 63 -; LMULMAX8-NEXT: ret +; LMULMAX1-RV64-LABEL: vreduce_add_v16i1: +; LMULMAX1-RV64: # %bb.0: +; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; LMULMAX1-RV64-NEXT: vcpop.m a0, v0 +; LMULMAX1-RV64-NEXT: slli a0, a0, 63 +; LMULMAX1-RV64-NEXT: srai a0, a0, 63 +; LMULMAX1-RV64-NEXT: ret +; +; LMULMAX8-RV32-LABEL: vreduce_add_v16i1: +; LMULMAX8-RV32: # %bb.0: +; LMULMAX8-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; LMULMAX8-RV32-NEXT: vcpop.m a0, v0 +; LMULMAX8-RV32-NEXT: slli a0, a0, 31 +; LMULMAX8-RV32-NEXT: srai a0, a0, 31 +; LMULMAX8-RV32-NEXT: ret +; +; LMULMAX8-RV64-LABEL: vreduce_add_v16i1: +; LMULMAX8-RV64: # %bb.0: +; LMULMAX8-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; LMULMAX8-RV64-NEXT: vcpop.m a0, v0 +; LMULMAX8-RV64-NEXT: slli a0, a0, 63 +; LMULMAX8-RV64-NEXT: srai a0, a0, 63 +; LMULMAX8-RV64-NEXT: ret %red = call i1 @llvm.vector.reduce.add.v16i1(<16 x i1> %v) ret i1 %red } @@ -1095,23 +1421,41 @@ define signext i1 @vreduce_add_v16i1(<16 x i1> %v) { declare i1 @llvm.vector.reduce.add.v32i1(<32 x i1>) define signext i1 @vreduce_add_v32i1(<32 x i1> %v) { -; LMULMAX1-LABEL: vreduce_add_v32i1: -; LMULMAX1: # %bb.0: -; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma -; LMULMAX1-NEXT: vmxor.mm v8, v0, v8 -; LMULMAX1-NEXT: vcpop.m a0, v8 -; LMULMAX1-NEXT: slli a0, a0, 31 -; LMULMAX1-NEXT: srai a0, a0, 31 -; LMULMAX1-NEXT: ret +; LMULMAX1-RV32-LABEL: vreduce_add_v32i1: +; LMULMAX1-RV32: # %bb.0: +; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; LMULMAX1-RV32-NEXT: vmxor.mm v8, v0, v8 +; LMULMAX1-RV32-NEXT: vcpop.m a0, v8 +; LMULMAX1-RV32-NEXT: slli a0, a0, 31 +; LMULMAX1-RV32-NEXT: srai a0, a0, 31 +; LMULMAX1-RV32-NEXT: ret ; -; LMULMAX8-LABEL: vreduce_add_v32i1: -; LMULMAX8: # %bb.0: -; LMULMAX8-NEXT: li a0, 32 -; LMULMAX8-NEXT: vsetvli zero, a0, e8, m2, ta, ma -; LMULMAX8-NEXT: vcpop.m a0, v0 -; LMULMAX8-NEXT: slli a0, a0, 63 -; LMULMAX8-NEXT: srai a0, a0, 63 -; LMULMAX8-NEXT: ret +; LMULMAX1-RV64-LABEL: vreduce_add_v32i1: +; LMULMAX1-RV64: # %bb.0: +; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; LMULMAX1-RV64-NEXT: vmxor.mm v8, v0, v8 +; LMULMAX1-RV64-NEXT: vcpop.m a0, v8 +; LMULMAX1-RV64-NEXT: slli a0, a0, 63 +; LMULMAX1-RV64-NEXT: srai a0, a0, 63 +; LMULMAX1-RV64-NEXT: ret +; +; LMULMAX8-RV32-LABEL: vreduce_add_v32i1: +; LMULMAX8-RV32: # %bb.0: +; LMULMAX8-RV32-NEXT: li a0, 32 +; LMULMAX8-RV32-NEXT: vsetvli zero, a0, e8, m2, ta, ma +; LMULMAX8-RV32-NEXT: vcpop.m a0, v0 +; LMULMAX8-RV32-NEXT: slli a0, a0, 31 +; LMULMAX8-RV32-NEXT: srai a0, a0, 31 +; LMULMAX8-RV32-NEXT: ret +; +; LMULMAX8-RV64-LABEL: vreduce_add_v32i1: +; LMULMAX8-RV64: # %bb.0: +; LMULMAX8-RV64-NEXT: li a0, 32 +; LMULMAX8-RV64-NEXT: vsetvli zero, a0, e8, m2, ta, ma +; LMULMAX8-RV64-NEXT: vcpop.m a0, v0 +; LMULMAX8-RV64-NEXT: slli a0, a0, 63 +; LMULMAX8-RV64-NEXT: srai a0, a0, 63 +; LMULMAX8-RV64-NEXT: ret %red = call i1 @llvm.vector.reduce.add.v32i1(<32 x i1> %v) ret i1 %red } @@ -1119,25 +1463,45 @@ define signext i1 @vreduce_add_v32i1(<32 x i1> %v) { declare i1 @llvm.vector.reduce.add.v64i1(<64 x i1>) define signext i1 @vreduce_add_v64i1(<64 x i1> %v) { -; LMULMAX1-LABEL: vreduce_add_v64i1: -; LMULMAX1: # %bb.0: -; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma -; LMULMAX1-NEXT: vmxor.mm v8, v8, v10 -; LMULMAX1-NEXT: vmxor.mm v9, v0, v9 -; LMULMAX1-NEXT: vmxor.mm v8, v9, v8 -; LMULMAX1-NEXT: vcpop.m a0, v8 -; LMULMAX1-NEXT: slli a0, a0, 31 -; LMULMAX1-NEXT: srai a0, a0, 31 -; LMULMAX1-NEXT: ret +; LMULMAX1-RV32-LABEL: vreduce_add_v64i1: +; LMULMAX1-RV32: # %bb.0: +; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; LMULMAX1-RV32-NEXT: vmxor.mm v8, v8, v10 +; LMULMAX1-RV32-NEXT: vmxor.mm v9, v0, v9 +; LMULMAX1-RV32-NEXT: vmxor.mm v8, v9, v8 +; LMULMAX1-RV32-NEXT: vcpop.m a0, v8 +; LMULMAX1-RV32-NEXT: slli a0, a0, 31 +; LMULMAX1-RV32-NEXT: srai a0, a0, 31 +; LMULMAX1-RV32-NEXT: ret ; -; LMULMAX8-LABEL: vreduce_add_v64i1: -; LMULMAX8: # %bb.0: -; LMULMAX8-NEXT: li a0, 64 -; LMULMAX8-NEXT: vsetvli zero, a0, e8, m4, ta, ma -; LMULMAX8-NEXT: vcpop.m a0, v0 -; LMULMAX8-NEXT: slli a0, a0, 63 -; LMULMAX8-NEXT: srai a0, a0, 63 -; LMULMAX8-NEXT: ret +; LMULMAX1-RV64-LABEL: vreduce_add_v64i1: +; LMULMAX1-RV64: # %bb.0: +; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; LMULMAX1-RV64-NEXT: vmxor.mm v8, v8, v10 +; LMULMAX1-RV64-NEXT: vmxor.mm v9, v0, v9 +; LMULMAX1-RV64-NEXT: vmxor.mm v8, v9, v8 +; LMULMAX1-RV64-NEXT: vcpop.m a0, v8 +; LMULMAX1-RV64-NEXT: slli a0, a0, 63 +; LMULMAX1-RV64-NEXT: srai a0, a0, 63 +; LMULMAX1-RV64-NEXT: ret +; +; LMULMAX8-RV32-LABEL: vreduce_add_v64i1: +; LMULMAX8-RV32: # %bb.0: +; LMULMAX8-RV32-NEXT: li a0, 64 +; LMULMAX8-RV32-NEXT: vsetvli zero, a0, e8, m4, ta, ma +; LMULMAX8-RV32-NEXT: vcpop.m a0, v0 +; LMULMAX8-RV32-NEXT: slli a0, a0, 31 +; LMULMAX8-RV32-NEXT: srai a0, a0, 31 +; LMULMAX8-RV32-NEXT: ret +; +; LMULMAX8-RV64-LABEL: vreduce_add_v64i1: +; LMULMAX8-RV64: # %bb.0: +; LMULMAX8-RV64-NEXT: li a0, 64 +; LMULMAX8-RV64-NEXT: vsetvli zero, a0, e8, m4, ta, ma +; LMULMAX8-RV64-NEXT: vcpop.m a0, v0 +; LMULMAX8-RV64-NEXT: slli a0, a0, 63 +; LMULMAX8-RV64-NEXT: srai a0, a0, 63 +; LMULMAX8-RV64-NEXT: ret %red = call i1 @llvm.vector.reduce.add.v64i1(<64 x i1> %v) ret i1 %red } -- 2.7.4