From 9b5563c52ca9412597b38c15b6f0c6225d95f8a1 Mon Sep 17 00:00:00 2001 From: Nirav Dave Date: Tue, 28 Mar 2017 14:11:20 +0000 Subject: [PATCH] [SDAG] Fix Stale SDNode usage in visitAND Reorder CombineTo Calls to prevent potential use of deleted node. Fixes PR32372. Reviewers: jnspaulsson, RKSimon, uweigand, jonpa Reviewed By: jonpa Subscribers: jonpa, llvm-commits Differential Revision: https://reviews.llvm.org/D31346 llvm-svn: 298920 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 8 +++---- llvm/test/CodeGen/SystemZ/pr32372.ll | 31 +++++++++++++++++++++++++++ 2 files changed, 35 insertions(+), 4 deletions(-) create mode 100644 llvm/test/CodeGen/SystemZ/pr32372.ll diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 2263ddc..c480c99 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -3536,6 +3536,10 @@ SDValue DAGCombiner::visitAND(SDNode *N) { // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to // preserve semantics once we get rid of the AND. SDValue NewLoad(Load, 0); + + // Fold the AND away. NewLoad may get replaced immediately. + CombineTo(N, NewLoad); + if (Load->getExtensionType() == ISD::EXTLOAD) { NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD, Load->getValueType(0), SDLoc(Load), @@ -3553,10 +3557,6 @@ SDValue DAGCombiner::visitAND(SDNode *N) { } } - // Fold the AND away, taking care not to fold to the old load node if we - // replaced it. - CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0); - return SDValue(N, 0); // Return N so it doesn't get rechecked! } } diff --git a/llvm/test/CodeGen/SystemZ/pr32372.ll b/llvm/test/CodeGen/SystemZ/pr32372.ll new file mode 100644 index 0000000..c18e238f --- /dev/null +++ b/llvm/test/CodeGen/SystemZ/pr32372.ll @@ -0,0 +1,31 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc %s -o - -mtriple=s390x-linux-gnu | FileCheck %s + +define void @pr32372(i8*) { +; CHECK-LABEL: pr32372: +; CHECK: # BB#0: # %BB +; CHECK-NEXT: llc %r1, 0(%r2) +; CHECK-NEXT: mvhhi 0(%r1), -3825 +; CHECK-NEXT: llill %r0, 0 +; CHECK-NEXT: dlr %r0, %r1 +; CHECK-NEXT: .LBB0_1: # %CF251 +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: j .LBB0_1 +BB: + %L = load i8, i8* %0 + store i16 -3825, i16* undef + %L5 = load i8, i8* %0 + %B9 = urem i8 %L5, %L + %I107 = insertelement <8 x i8> zeroinitializer, i8 %B9, i32 7 + %ZE141 = zext i8 %L5 to i16 + br label %CF251 + +CF251: ; preds = %CF258, %CF251, %BB + %Shuff217 = shufflevector <8 x i8> zeroinitializer, <8 x i8> %I107, <8 x i32> + %Cmp227 = icmp sge i16 %ZE141, 0 + br i1 %Cmp227, label %CF251, label %CF258 + +CF258: ; preds = %CF251 + %Shuff230 = shufflevector <2 x i16> undef, <2 x i16> undef, <2 x i32> + br label %CF251 +} -- 2.7.4