From 9b4247de4f578102b00513f59596dc8e15d34c15 Mon Sep 17 00:00:00 2001 From: Sudakshina Das Date: Wed, 9 Jan 2019 14:08:01 +0000 Subject: [PATCH] [AArch64, 2/6] Add new arch command line feaures from ARMv8.5-A This patch is part of a series that enables ARMv8.5-A in GCC and adds Branch Target Identification Mechanism. This patch add all the command line feature that are added by ARMv8.5. Optional extensions to armv8.5-a: +rng : Random number Generation Instructions. +memtag : Memory Tagging Extension. ARMv8.5-A features that are optional to older arch: +sb : Speculation barrier instruction. +ssbs: Speculative Store Bypass Safe instruction. +predres: Execution and Data Prediction Restriction instructions. All of the above only effect the assembler and have already gone in the trunk of binutils. *** gcc/ChangeLog *** 2018-01-09 Sudakshina Das * config/aarch64/aarch64-option-extensions.def: Define AARCH64_OPT_EXTENSION for memtag, rng, sb, ssbs and predres. * gcc/config/aarch64/aarch64.h (AARCH64_FL_RNG): New. (AARCH64_FL_MEMTAG, ARCH64_FL_SB, AARCH64_FL_SSBS): New. (AARCH64_FL_PREDRES): New. (AARCH64_FL_FOR_ARCH8_5): Add AARCH64_FL_SB, AARCH64_FL_SSBS and AARCH64_FL_PREDRES by default. * gcc/doc/invoke.texi: Document rng, memtag, sb, ssbs and predres. From-SVN: r267766 --- gcc/ChangeLog | 11 +++++++++++ gcc/config/aarch64/aarch64-option-extensions.def | 15 +++++++++++++++ gcc/config/aarch64/aarch64.h | 15 ++++++++++++++- gcc/doc/invoke.texi | 21 +++++++++++++++++++++ 4 files changed, 61 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5aa91ca..99f9022 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,16 @@ 2018-01-09 Sudakshina Das + * config/aarch64/aarch64-option-extensions.def: Define + AARCH64_OPT_EXTENSION for memtag, rng, sb, ssbs and predres. + * gcc/config/aarch64/aarch64.h (AARCH64_FL_RNG): New. + (AARCH64_FL_MEMTAG, ARCH64_FL_SB, AARCH64_FL_SSBS): New. + (AARCH64_FL_PREDRES): New. + (AARCH64_FL_FOR_ARCH8_5): Add AARCH64_FL_SB, AARCH64_FL_SSBS and + AARCH64_FL_PREDRES by default. + * gcc/doc/invoke.texi: Document rng, memtag, sb, ssbs and predres. + +2018-01-09 Sudakshina Das + * config/aarch64/aarch64-arches.def: Define AARCH64_ARCH for ARMv8.5-A. * gcc/config/aarch64/aarch64.h (AARCH64_FL_V8_5): New. diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def index 12b390d..2879e35 100644 --- a/gcc/config/aarch64/aarch64-option-extensions.def +++ b/gcc/config/aarch64/aarch64-option-extensions.def @@ -108,4 +108,19 @@ AARCH64_OPT_EXTENSION("sve", AARCH64_FL_SVE, AARCH64_FL_FP | AARCH64_FL_SIMD | A /* Enabling/Disabling "profile" does not enable/disable any other feature. */ AARCH64_OPT_EXTENSION("profile", AARCH64_FL_PROFILE, 0, 0, "") +/* Enabling/Disabling "rng" only changes "rng". */ +AARCH64_OPT_EXTENSION("rng", AARCH64_FL_RNG, 0, 0, "") + +/* Enabling/Disabling "memtag" only changes "memtag". */ +AARCH64_OPT_EXTENSION("memtag", AARCH64_FL_MEMTAG, 0, 0, "") + +/* Enabling/Disabling "sb" only changes "sb". */ +AARCH64_OPT_EXTENSION("sb", AARCH64_FL_SB, 0, 0, "") + +/* Enabling/Disabling "ssbs" only changes "ssbs". */ +AARCH64_OPT_EXTENSION("ssbs", AARCH64_FL_SSBS, 0, 0, "") + +/* Enabling/Disabling "predres" only changes "predres". */ +AARCH64_OPT_EXTENSION("predres", AARCH64_FL_PREDRES, 0, 0, "") + #undef AARCH64_OPT_EXTENSION diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index 1d8a0ef..10e73bb 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -179,6 +179,18 @@ extern unsigned aarch64_architecture_version; /* ARMv8.5-A architecture extensions. */ #define AARCH64_FL_V8_5 (1 << 22) /* Has ARMv8.5-A features. */ +#define AARCH64_FL_RNG (1 << 23) /* ARMv8.5-A Random Number Insns. */ +#define AARCH64_FL_MEMTAG (1 << 24) /* ARMv8.5-A Memory Tagging + Extensions. */ + +/* Speculation Barrier instruction supported. */ +#define AARCH64_FL_SB (1 << 25) + +/* Speculative Store Bypass Safe instruction supported. */ +#define AARCH64_FL_SSBS (1 << 26) + +/* Execution and Data Prediction Restriction instructions supported. */ +#define AARCH64_FL_PREDRES (1 << 27) /* Has FP and SIMD. */ #define AARCH64_FL_FPSIMD (AARCH64_FL_FP | AARCH64_FL_SIMD) @@ -199,7 +211,8 @@ extern unsigned aarch64_architecture_version; (AARCH64_FL_FOR_ARCH8_3 | AARCH64_FL_V8_4 | AARCH64_FL_F16FML \ | AARCH64_FL_DOTPROD | AARCH64_FL_RCPC8_4) #define AARCH64_FL_FOR_ARCH8_5 \ - (AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_V8_5) + (AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_V8_5 \ + | AARCH64_FL_SB | AARCH64_FL_SSBS | AARCH64_FL_PREDRES) /* Macros to test ISA flags. */ diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index f2d11e8..c7c80f7 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -15836,6 +15836,27 @@ Use of this option with architectures prior to Armv8.2-A is not supported. @item profile Enable the Statistical Profiling extension. This option is only to enable the extension at the assembler level and does not affect code generation. +@item rng +Enable the Armv8.5-a Random Number instructions. This option is only to +enable the extension at the assembler level and does not affect code +generation. +@item memtag +Enable the Armv8.5-a Memory Tagging Extensions. This option is only to +enable the extension at the assembler level and does not affect code +generation. +@item sb +Enable the Armv8-a Speculation Barrier instruction. This option is only to +enable the extension at the assembler level and does not affect code +generation. This option is enabled by default for @option{-march=armv8.5-a}. +@item ssbs +Enable the Armv8-a Speculative Store Bypass Safe instruction. This option +is only to enable the extension at the assembler level and does not affect code +generation. This option is enabled by default for @option{-march=armv8.5-a}. +@item predres +Enable the Armv8-a Execution and Data Prediction Restriction instructions. +This option is only to enable the extension at the assembler level and does +not affect code generation. This option is enabled by default for +@option{-march=armv8.5-a}. @end table -- 2.7.4