From 9b2d84058445ae826548e2ba4f08b551b251d06f Mon Sep 17 00:00:00 2001 From: =?utf8?q?Lothar=20Wa=C3=9Fmann?= Date: Tue, 17 Oct 2017 11:17:57 +0200 Subject: [PATCH] ARM: dts: imx6-tx6: specify ethernet phy reset post-delay MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Under certain circumstances the ethernet PHY cannot be detected on Ka-Ro electronics TX6 modules. Using a phy-reset-post-delay of at least 2ms alleviates this problem. Define it to 10ms to be on the safe side. Signed-off-by: Lothar Waßmann Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-tx6.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/imx6qdl-tx6.dtsi index f2cd3e7..f1655b3 100644 --- a/arch/arm/boot/dts/imx6qdl-tx6.dtsi +++ b/arch/arm/boot/dts/imx6qdl-tx6.dtsi @@ -249,6 +249,7 @@ clock-names = "ipg", "ahb", "ptp", "enet_out"; phy-mode = "rmii"; phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; + phy-reset-post-delay = <10>; phy-handle = <&etnphy>; phy-supply = <®_3v3_etn>; status = "okay"; -- 2.7.4