From 9b20c245ca36998cb2ac6e81543f87b781a9d06b Mon Sep 17 00:00:00 2001 From: "Ivan A. Kosarev" Date: Thu, 19 Apr 2018 15:27:28 +0000 Subject: [PATCH] [NEON] Define vfma_n_f32() and vfmaq_n_f32() intrinsics in AArch32 mode Differential Revision: https://reviews.llvm.org/D45670 llvm-svn: 330336 --- clang/include/clang/Basic/arm_neon.td | 3 ++- clang/test/CodeGen/arm-neon-fma.c | 24 ++++++++++++++++++++++++ 2 files changed, 26 insertions(+), 1 deletion(-) diff --git a/clang/include/clang/Basic/arm_neon.td b/clang/include/clang/Basic/arm_neon.td index 0e3be38..162da91 100644 --- a/clang/include/clang/Basic/arm_neon.td +++ b/clang/include/clang/Basic/arm_neon.td @@ -531,6 +531,7 @@ def VREINTERPRET let ArchGuard = "defined(__ARM_FEATURE_FMA)" in { def VFMA : SInst<"vfma", "dddd", "fQf">; def VFMS : SOpInst<"vfms", "dddd", "fQf", OP_FMLS>; + def FMLA_N_F32 : SOpInst<"vfma_n", "ddds", "fQf", OP_FMLA_N>; } //////////////////////////////////////////////////////////////////////////////// @@ -621,7 +622,7 @@ def FMLS : SOpInst<"vfms", "dddd", "dQd", OP_FMLS>; // MUL, MLA, MLS, FMA, FMS definitions with scalar argument def VMUL_N_A64 : IOpInst<"vmul_n", "dds", "Qd", OP_MUL_N>; -def FMLA_N : SOpInst<"vfma_n", "ddds", "fdQfQd", OP_FMLA_N>; +def FMLA_N : SOpInst<"vfma_n", "ddds", "dQd", OP_FMLA_N>; def FMLS_N : SOpInst<"vfms_n", "ddds", "fdQfQd", OP_FMLS_N>; def MLA_N : SOpInst<"vmla_n", "ddds", "Qd", OP_MLA_N>; diff --git a/clang/test/CodeGen/arm-neon-fma.c b/clang/test/CodeGen/arm-neon-fma.c index b5184c1..5f6737a 100644 --- a/clang/test/CodeGen/arm-neon-fma.c +++ b/clang/test/CodeGen/arm-neon-fma.c @@ -20,3 +20,27 @@ float32x2_t test_fma_order(float32x2_t accum, float32x2_t lhs, float32x2_t rhs) float32x4_t test_fmaq_order(float32x4_t accum, float32x4_t lhs, float32x4_t rhs) { return vfmaq_f32(accum, lhs, rhs); } + +// CHECK-LABEL: define <2 x float> @test_vfma_n_f32(<2 x float> %a, <2 x float> %b, float %n) #0 { +// CHECK: [[VECINIT_I:%.*]] = insertelement <2 x float> undef, float %n, i32 0 +// CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x float> [[VECINIT_I]], float %n, i32 1 +// CHECK: [[TMP1:%.*]] = bitcast <2 x float> %b to <8 x i8> +// CHECK: [[TMP2:%.*]] = bitcast <2 x float> [[VECINIT1_I]] to <8 x i8> +// CHECK: [[TMP3:%.*]] = call <2 x float> @llvm.fma.v2f32(<2 x float> %b, <2 x float> [[VECINIT1_I]], <2 x float> %a) +// CHECK: ret <2 x float> [[TMP3]] +float32x2_t test_vfma_n_f32(float32x2_t a, float32x2_t b, float32_t n) { + return vfma_n_f32(a, b, n); +} + +// CHECK-LABEL: define <4 x float> @test_vfmaq_n_f32(<4 x float> %a, <4 x float> %b, float %n) #0 { +// CHECK: [[VECINIT_I:%.*]] = insertelement <4 x float> undef, float %n, i32 0 +// CHECK: [[VECINIT1_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], float %n, i32 1 +// CHECK: [[VECINIT2_I:%.*]] = insertelement <4 x float> [[VECINIT1_I]], float %n, i32 2 +// CHECK: [[VECINIT3_I:%.*]] = insertelement <4 x float> [[VECINIT2_I]], float %n, i32 3 +// CHECK: [[TMP1:%.*]] = bitcast <4 x float> %b to <16 x i8> +// CHECK: [[TMP2:%.*]] = bitcast <4 x float> [[VECINIT3_I]] to <16 x i8> +// CHECK: [[TMP3:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %b, <4 x float> [[VECINIT3_I]], <4 x float> %a) +// CHECK: ret <4 x float> [[TMP3]] +float32x4_t test_vfmaq_n_f32(float32x4_t a, float32x4_t b, float32_t n) { + return vfmaq_n_f32(a, b, n); +} -- 2.7.4