From 9b11bbf0c4008fa0b715ed68db0d5669175413c5 Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Wed, 4 Mar 2020 15:31:44 +0000 Subject: [PATCH] drm/i915/tgl: WaDisableGPGPUMidThreadPreemption MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Enable FtrPerCtxtPreemptionGranularityControl bit and select thread- group as the default preemption level. v2: * Remove register whitelisting (Rafael, Tony). Signed-off-by: Tvrtko Ursulin Cc: Michał Winiarski Cc: Joonas Lahtinen Cc: piotr.zdunowski@intel.com Cc: michal.mrozek@intel.com Cc: Tony Ye Cc: Rafael Antognolli Acked-by: Rafael Antognolli Acked-by: Jason Ekstrand Acked-by: Chris Wilson Acked-by: Tony Ye Link: https://patchwork.freedesktop.org/patch/msgid/20200304153144.10675-1-tvrtko.ursulin@linux.intel.com --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index cb7d85c..7be71a1 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -601,6 +601,11 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, */ wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, FF_MODE2_TDS_TIMER_128, 0); + + /* WaDisableGPGPUMidThreadPreemption:tgl */ + WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, + GEN9_PREEMPT_GPGPU_LEVEL_MASK, + GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); } static void @@ -1475,8 +1480,8 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) PSDUNIT_CLKGATE_DIS); } - if (IS_GEN_RANGE(i915, 9, 11)) { - /* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl */ + if (IS_GEN_RANGE(i915, 9, 12)) { + /* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl,tgl */ wa_masked_en(wal, GEN7_FF_SLICE_CS_CHICKEN1, GEN9_FFSC_PERCTX_PREEMPT_CTRL); -- 2.7.4