From 9aa60213403b12f2ef393a62b52064a2211cc320 Mon Sep 17 00:00:00 2001 From: Likun Gao Date: Fri, 6 Mar 2020 17:01:22 +0800 Subject: [PATCH] drm/amd/powerplay: Enable SOCCLK ULV for sienna_cichlid Enable FW DSTATE for sienna_cichlid. Enable DF CSTATE for sienna_cichlid. Signed-off-by: Likun Gao Reviewed-by: Kenneth Feng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c index 49e157f2b39f..a91e6f753bea 100644 --- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c @@ -272,6 +272,8 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu, *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT) + | FEATURE_MASK(FEATURE_FW_DSTATE_BIT) + | FEATURE_MASK(FEATURE_DF_CSTATE_BIT) | FEATURE_MASK(FEATURE_THERMAL_BIT); if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) -- 2.34.1