From 9a5a1e278f91fd7e67fdfbdb8d2f2f72dd566c99 Mon Sep 17 00:00:00 2001 From: Pat Haugen Date: Wed, 3 Mar 2021 17:54:30 -0600 Subject: [PATCH] Update size attribute for Power10. 2021-03-03 Pat Haugen gcc/ * config/rs6000/dfp.md (extendddtd2, trunctddd2, *cmp_internal1, floatditd2, ftrunc2, fixdi2, dfp_ddedpd_, dfp_denbcd_, dfp_dxex_, dfp_diex_, *dfp_sgnfcnc_, dfp_dscli_, dfp_dscri_): Update size attribute for Power10. * config/rs6000/mma.md (*movoo): Likewise. * config/rs6000/rs6000.md (define_attr "size"): Add 256. (define_mode_attr bits): Add DD/TD modes. * config/rs6000/sync.md (load_quadpti, store_quadpti, load_lockedpti, store_conditionalpti): Update size attribute for Power10. --- gcc/config/rs6000/dfp.md | 37 +++++++++++++++++++++++++------------ gcc/config/rs6000/mma.md | 1 + gcc/config/rs6000/rs6000.md | 3 ++- gcc/config/rs6000/sync.md | 8 ++++++-- 4 files changed, 34 insertions(+), 15 deletions(-) diff --git a/gcc/config/rs6000/dfp.md b/gcc/config/rs6000/dfp.md index c8cdb64..026be5d 100644 --- a/gcc/config/rs6000/dfp.md +++ b/gcc/config/rs6000/dfp.md @@ -139,7 +139,8 @@ (float_extend:TD (match_operand:DD 1 "gpc_reg_operand" "d")))] "TARGET_DFP" "dctqpq %0,%1" - [(set_attr "type" "dfp")]) + [(set_attr "type" "dfp") + (set_attr "size" "128")]) ;; The result of drdpq is an even/odd register pair with the converted ;; value in the even register and zero in the odd register. @@ -153,6 +154,7 @@ "TARGET_DFP" "drdpq %2,%1\;fmr %0,%2" [(set_attr "type" "dfp") + (set_attr "size" "128") (set_attr "length" "8")]) (define_insn "trunctdsd2" @@ -206,7 +208,8 @@ (match_operand:DDTD 2 "gpc_reg_operand" "d")))] "TARGET_DFP" "dcmpu %0,%1,%2" - [(set_attr "type" "dfp")]) + [(set_attr "type" "dfp") + (set_attr "size" "")]) (define_insn "floatdidd2" [(set (match_operand:DD 0 "gpc_reg_operand" "=d") @@ -220,7 +223,8 @@ (float:TD (match_operand:DI 1 "gpc_reg_operand" "d")))] "TARGET_DFP" "dcffixq %0,%1" - [(set_attr "type" "dfp")]) + [(set_attr "type" "dfp") + (set_attr "size" "128")]) ;; Convert a decimal64/128 to a decimal64/128 whose value is an integer. ;; This is the first stage of converting it to an integer type. @@ -230,7 +234,8 @@ (fix:DDTD (match_operand:DDTD 1 "gpc_reg_operand" "d")))] "TARGET_DFP" "drintn. 0,%0,%1,1" - [(set_attr "type" "dfp")]) + [(set_attr "type" "dfp") + (set_attr "size" "")]) ;; Convert a decimal64/128 whose value is an integer to an actual integer. ;; This is the second stage of converting decimal float to integer type. @@ -240,7 +245,8 @@ (fix:DI (match_operand:DDTD 1 "gpc_reg_operand" "d")))] "TARGET_DFP" "dctfix %0,%1" - [(set_attr "type" "dfp")]) + [(set_attr "type" "dfp") + (set_attr "size" "")]) ;; Decimal builtin support @@ -262,7 +268,8 @@ UNSPEC_DDEDPD))] "TARGET_DFP" "ddedpd %1,%0,%2" - [(set_attr "type" "dfp")]) + [(set_attr "type" "dfp") + (set_attr "size" "")]) (define_insn "dfp_denbcd_" [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d") @@ -271,7 +278,8 @@ UNSPEC_DENBCD))] "TARGET_DFP" "denbcd %1,%0,%2" - [(set_attr "type" "dfp")]) + [(set_attr "type" "dfp") + (set_attr "size" "")]) (define_insn "dfp_denbcd_v16qi_inst" [(set (match_operand:TD 0 "gpc_reg_operand" "=d") @@ -301,7 +309,8 @@ UNSPEC_DXEX))] "TARGET_DFP" "dxex %0,%1" - [(set_attr "type" "dfp")]) + [(set_attr "type" "dfp") + (set_attr "size" "")]) (define_insn "dfp_diex_" [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d") @@ -310,7 +319,8 @@ UNSPEC_DXEX))] "TARGET_DFP" "diex %0,%1,%2" - [(set_attr "type" "dfp")]) + [(set_attr "type" "dfp") + (set_attr "size" "")]) (define_expand "dfptstsfi__" [(set (match_dup 3) @@ -349,7 +359,8 @@ operands[1] = GEN_INT (63); return "dtstsfi %0,%1,%2"; } - [(set_attr "type" "fp")]) + [(set_attr "type" "fp") + (set_attr "size" "")]) (define_insn "dfp_dscli_" [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d") @@ -358,7 +369,8 @@ UNSPEC_DSCLI))] "TARGET_DFP" "dscli %0,%1,%2" - [(set_attr "type" "dfp")]) + [(set_attr "type" "dfp") + (set_attr "size" "")]) (define_insn "dfp_dscri_" [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d") @@ -367,4 +379,5 @@ UNSPEC_DSCRI))] "TARGET_DFP" "dscri %0,%1,%2" - [(set_attr "type" "dfp")]) + [(set_attr "type" "dfp") + (set_attr "size" "")]) diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md index c40501f..a00d3a3 100644 --- a/gcc/config/rs6000/mma.md +++ b/gcc/config/rs6000/mma.md @@ -288,6 +288,7 @@ DONE; } [(set_attr "type" "vecload,vecstore,veclogical") + (set_attr "size" "256") (set_attr "length" "*,*,8")]) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index a1904b3..c0d7b1a 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -209,7 +209,7 @@ ;; What data size does this instruction work on? ;; This is used for insert, mul and others as necessary. -(define_attr "size" "8,16,32,64,128" (const_string "32")) +(define_attr "size" "8,16,32,64,128,256" (const_string "32")) ;; What is the insn_cost for this insn? The target hook can still override ;; this. For optimizing for size the "length" attribute is used instead. @@ -675,6 +675,7 @@ ;; How many bits (per element) in this mode? (define_mode_attr bits [(QI "8") (HI "16") (SI "32") (DI "64") (SF "32") (DF "64") + (DD "64") (TD "128") (V4SI "32") (V2DI "64")]) ; DImode bits diff --git a/gcc/config/rs6000/sync.md b/gcc/config/rs6000/sync.md index 11e4c03..40629dd 100644 --- a/gcc/config/rs6000/sync.md +++ b/gcc/config/rs6000/sync.md @@ -131,6 +131,7 @@ && !reg_mentioned_p (operands[0], operands[1])" "lq %0,%1" [(set_attr "type" "load") + (set_attr "size" "128") (set (attr "prefixed") (if_then_else (match_test "TARGET_PREFIXED") (const_string "yes") (const_string "no")))]) @@ -205,6 +206,7 @@ "TARGET_SYNC_TI" "stq %1,%0" [(set_attr "type" "store") + (set_attr "size" "128") (set (attr "prefixed") (if_then_else (match_test "TARGET_PREFIXED") (const_string "yes") (const_string "no")))]) @@ -333,7 +335,8 @@ && !reg_mentioned_p (operands[0], operands[1]) && quad_int_reg_operand (operands[0], PTImode)" "lqarx %0,%y1" - [(set_attr "type" "load_l")]) + [(set_attr "type" "load_l") + (set_attr "size" "128")]) (define_insn "store_conditional" [(set (match_operand:CC 0 "cc_reg_operand" "=x") @@ -394,7 +397,8 @@ (match_operand:PTI 2 "quad_int_reg_operand" "r"))] "TARGET_SYNC_TI && quad_int_reg_operand (operands[2], PTImode)" "stqcx. %2,%y1" - [(set_attr "type" "store_c")]) + [(set_attr "type" "store_c") + (set_attr "size" "128")]) (define_expand "atomic_compare_and_swap" [(match_operand:SI 0 "int_reg_operand") ;; bool out -- 2.7.4