From 9a4641cf6b669598d270117e5c64653db6e7db65 Mon Sep 17 00:00:00 2001 From: Faith Ekstrand Date: Fri, 24 Feb 2023 18:04:49 -0600 Subject: [PATCH] intel/nir: Limit unaligned loads to vec4 This probably doesn't affect Vulkan or GL because they can't have anything bigger than a vec4 anyway unless it's a u64vec4 and those have to be at least 8B aligned. This may affect CL apps if they use __attribute__((packed)) on something with big vectors, depending on how LLVM decides to translate that. Fixes: f8aa83f0c86e ("intel/nir: Use nir_lower_mem_access_bit_sizes()") Part-of: --- src/intel/compiler/brw_nir.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index 71f8e10..7a0c765 100644 --- a/src/intel/compiler/brw_nir.c +++ b/src/intel/compiler/brw_nir.c @@ -1279,7 +1279,7 @@ get_mem_access_size_align(nir_intrinsic_op intrin, uint8_t bytes, if (align < 4 && offset_is_const) { assert(util_is_power_of_two_nonzero(align_mul) && align_mul >= 4); const unsigned pad = align_offset % 4; - const unsigned comps32 = DIV_ROUND_UP(bytes + pad, 4); + const unsigned comps32 = MIN2(DIV_ROUND_UP(bytes + pad, 4), 4); return (nir_mem_access_size_align) { .bit_size = 32, .num_components = comps32, -- 2.7.4