From 9a072c19ae35ab827c489fc041dda207bcf8960a Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Tue, 18 Nov 2014 23:57:33 +0000
Subject: [PATCH] R600/SI: Set hasSideEffects = 0 on load and store
 instructions.

Assuming unmodeled side effects interferes with some scheduling
opportunities.

Don't put it in the base class of DS instructions since there
are a few weird effecting, non load/store instructions there.

llvm-svn: 222285
---
 llvm/lib/Target/R600/SIInstrFormats.td | 8 +++++---
 llvm/lib/Target/R600/SIInstrInfo.td    | 5 ++++-
 2 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/Target/R600/SIInstrFormats.td b/llvm/lib/Target/R600/SIInstrFormats.td
index bc8c011..10e0a3f 100644
--- a/llvm/lib/Target/R600/SIInstrFormats.td
+++ b/llvm/lib/Target/R600/SIInstrFormats.td
@@ -223,6 +223,7 @@ class SMRD <dag outs, dag ins, string asm, list<dag> pattern> :
   let SMRD = 1;
   let mayStore = 0;
   let mayLoad = 1;
+  let hasSideEffects = 0;
   let UseNamedOperandTable = 1;
 }
 
@@ -527,10 +528,9 @@ class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> :
 
 class VINTRP <bits <2> op, dag outs, dag ins, string asm, list<dag> pattern> :
     InstSI <outs, ins, asm, pattern>, VINTRPe<op> {
-
-  let neverHasSideEffects = 1;
   let mayLoad = 1;
   let mayStore = 0;
+  let hasSideEffects = 0;
 }
 
 } // End Uses = [EXEC]
@@ -555,7 +555,7 @@ class MUBUF <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
   let EXP_CNT = 1;
   let MUBUF = 1;
 
-  let neverHasSideEffects = 1;
+  let hasSideEffects = 0;
   let UseNamedOperandTable = 1;
 }
 
@@ -591,6 +591,8 @@ class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
   let VM_CNT = 1;
   let EXP_CNT = 1;
   let MIMG = 1;
+
+  let hasSideEffects = 0; // XXX ????
 }
 
 
diff --git a/llvm/lib/Target/R600/SIInstrInfo.td b/llvm/lib/Target/R600/SIInstrInfo.td
index 2c9ffaf..713e84e 100644
--- a/llvm/lib/Target/R600/SIInstrInfo.td
+++ b/llvm/lib/Target/R600/SIInstrInfo.td
@@ -941,6 +941,8 @@ class DS_1A <bits<8> op, dag outs, dag ins, string asm, list<dag> pat> :
   // Single load interpret the 2 i8imm operands as a single i16 offset.
   let offset0 = offset{7-0};
   let offset1 = offset{15-8};
+
+  let hasSideEffects = 0;
 }
 
 class DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
@@ -965,6 +967,7 @@ class DS_Load2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
   let data1 = 0;
   let mayLoad = 1;
   let mayStore = 0;
+  let hasSideEffects = 0;
 }
 
 class DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
@@ -988,6 +991,7 @@ class DS_Store2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
   []> {
   let mayStore = 1;
   let mayLoad = 0;
+  let hasSideEffects = 0;
   let vdst = 0;
 }
 
@@ -1016,7 +1020,6 @@ class DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc, string noRetOp = ""
   AtomicNoRet<noRetOp, 1> {
   let mayStore = 1;
   let mayLoad = 1;
-
   let hasPostISelHook = 1; // Adjusted to no return version.
 }
 
-- 
2.7.4