From 99c1acf3f1df46fea196f57fe2e145792fa5084d Mon Sep 17 00:00:00 2001
From: jacquesguan <jacquesguan@me.com>
Date: Fri, 7 Jan 2022 16:53:02 +0800
Subject: [PATCH] [RISCV] Add precommit test for select vl op that equal to ~0.

Precommit test for D116798

Differential Revision: https://reviews.llvm.org/D116799
---
 llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
index c8c50ac..c7c9bcf 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
@@ -239,6 +239,21 @@ entry:
   ret <vscale x 1 x double> %y
 }
 
+define <vscale x 1 x double> @test13(<vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
+; CHECK-LABEL: test13:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    li a0, -1
+; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, mu
+; CHECK-NEXT:    vfadd.vv v8, v8, v9
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(
+    <vscale x 1 x double> %a,
+    <vscale x 1 x double> %b,
+    i64 -1)
+  ret <vscale x 1 x double> %0
+}
+
 declare <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.nxv1i64(
   <vscale x 1 x i64>,
   <vscale x 1 x i64>,
-- 
2.7.4