From 99981689821ea1fe41c06613f58110d4413a702f Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Sat, 14 Feb 2015 02:55:56 +0000 Subject: [PATCH] R600/SI: Fix copies from SGPR to VCC This shows up without optimizations when vcc is required to be used. llvm-svn: 229226 --- llvm/lib/Target/R600/SIInstrInfo.cpp | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/llvm/lib/Target/R600/SIInstrInfo.cpp b/llvm/lib/Target/R600/SIInstrInfo.cpp index 13775b5..8b65d5c 100644 --- a/llvm/lib/Target/R600/SIInstrInfo.cpp +++ b/llvm/lib/Target/R600/SIInstrInfo.cpp @@ -333,12 +333,17 @@ SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB, } else if (AMDGPU::SReg_64RegClass.contains(DestReg)) { if (DestReg == AMDGPU::VCC) { - // FIXME: Hack until VReg_1 removed. + if (AMDGPU::SReg_64RegClass.contains(SrcReg)) { + BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), AMDGPU::VCC) + .addReg(SrcReg, getKillRegState(KillSrc)); + } else { + // FIXME: Hack until VReg_1 removed. + assert(AMDGPU::VGPR_32RegClass.contains(SrcReg)); + BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_I32_e32), AMDGPU::VCC) + .addImm(0) + .addReg(SrcReg, getKillRegState(KillSrc)); + } - assert(AMDGPU::VGPR_32RegClass.contains(SrcReg)); - BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_I32_e32), AMDGPU::VCC) - .addImm(0) - .addReg(SrcReg, getKillRegState(KillSrc)); return; } -- 2.7.4