From 994a43d27a7e844f569816f4947a8c4031f73cbc Mon Sep 17 00:00:00 2001 From: NAKAMURA Takumi Date: Tue, 16 May 2017 04:01:23 +0000 Subject: [PATCH] AMDGPUCodeGen: Fix warnings in r303111. [-Wunused-variable] llvm-svn: 303137 --- llvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp | 2 ++ llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp b/llvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp index ab8b137..6d2785b 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp @@ -136,9 +136,11 @@ void PHILinearize::phiInfoElementAddSource(PHIInfoElementT *Info, // sources, because we cannot have different registers with // identical predecessors, but we can have the same register for // multiple predecessors. +#if !defined(NDEBUG) for (auto SI : phiInfoElementGetSources(Info)) { assert((SI.second != SourceMBB || SourceReg == SI.first)); } +#endif phiInfoElementGetSources(Info).insert(PHISourceT(SourceReg, SourceMBB)); } diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index c87b042..065fd09 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -564,8 +564,8 @@ void SIInstrInfo::insertVectorSelect(MachineBasicBlock &MBB, unsigned TrueReg, unsigned FalseReg) const { MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); - const TargetRegisterClass *RegClass = MRI.getRegClass(DstReg); - assert(RegClass == &AMDGPU::VGPR_32RegClass && "Not a VGPR32 reg"); + assert(MRI.getRegClass(DstReg) == &AMDGPU::VGPR_32RegClass && + "Not a VGPR32 reg"); if (Cond.size() == 1) { BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg) -- 2.7.4