From 989ebc1783a591630f142d41fd59bb57a6942be4 Mon Sep 17 00:00:00 2001 From: wanglian Date: Thu, 18 Aug 2022 15:09:21 +0800 Subject: [PATCH] [DAGCombiner][NFC] Tidy up unnecessary brackets in visitADD. Reviewed By: sdesmalen Differential Revision: https://reviews.llvm.org/D132107 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 1739f18..56beea3 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -2672,9 +2672,9 @@ SDValue DAGCombiner::visitADD(SDNode *N) { } // fold a+vscale(c1)+vscale(c2) -> a+vscale(c1+c2) - if ((N0.getOpcode() == ISD::ADD) && - (N0.getOperand(1).getOpcode() == ISD::VSCALE) && - (N1.getOpcode() == ISD::VSCALE)) { + if (N0.getOpcode() == ISD::ADD && + N0.getOperand(1).getOpcode() == ISD::VSCALE && + N1.getOpcode() == ISD::VSCALE) { const APInt &VS0 = N0.getOperand(1)->getConstantOperandAPInt(0); const APInt &VS1 = N1->getConstantOperandAPInt(0); SDValue VS = DAG.getVScale(DL, VT, VS0 + VS1); @@ -2691,9 +2691,9 @@ SDValue DAGCombiner::visitADD(SDNode *N) { } // Fold a + step_vector(c1) + step_vector(c2) to a + step_vector(c1+c2) - if ((N0.getOpcode() == ISD::ADD) && - (N0.getOperand(1).getOpcode() == ISD::STEP_VECTOR) && - (N1.getOpcode() == ISD::STEP_VECTOR)) { + if (N0.getOpcode() == ISD::ADD && + N0.getOperand(1).getOpcode() == ISD::STEP_VECTOR && + N1.getOpcode() == ISD::STEP_VECTOR) { const APInt &SV0 = N0.getOperand(1)->getConstantOperandAPInt(0); const APInt &SV1 = N1->getConstantOperandAPInt(0); APInt NewStep = SV0 + SV1; -- 2.7.4