From 987bd298f8d67ff56da1c38fd4a16bf02f77a909 Mon Sep 17 00:00:00 2001 From: Andrew Au Date: Mon, 13 Aug 2018 14:53:10 -0700 Subject: [PATCH] Fix ARM compilation issue Commit migrated from https://github.com/dotnet/coreclr/commit/7e94efe87f48b990e77e87f6f643cdf1ab51f951 --- src/coreclr/src/debug/ee/controller.h | 4 ++-- src/coreclr/src/inc/cordebug.idl | 1 + src/coreclr/src/pal/prebuilt/inc/cordebug.h | 32 +++++++++++++++++++++++++++++ 3 files changed, 35 insertions(+), 2 deletions(-) diff --git a/src/coreclr/src/debug/ee/controller.h b/src/coreclr/src/debug/ee/controller.h index 4d91d7d..7084bd9 100644 --- a/src/coreclr/src/debug/ee/controller.h +++ b/src/coreclr/src/debug/ee/controller.h @@ -1815,7 +1815,7 @@ public: LOG((LF_CORDB, LL_INFO10000, "D::DDBP: Doing TriggerDataBreakpoint...\n")); bool hitDataBp = false; - +#if defined(_TARGET_X86_) || defined(_TARGET_AMD64_) PDR6 pdr6 = (PDR6)&(pContext->Dr6); if (pdr6->B0 || pdr6->B1 || pdr6->B2 || pdr6->B3) @@ -1831,7 +1831,7 @@ public: { LOG((LF_CORDB, LL_INFO10000, "D::DDBP: DIDN'T TRIGGER DATA BREAKPOINT...\n")); } - +#endif return hitDataBp; } diff --git a/src/coreclr/src/inc/cordebug.idl b/src/coreclr/src/inc/cordebug.idl index 0fd1588..c23f305 100644 --- a/src/coreclr/src/inc/cordebug.idl +++ b/src/coreclr/src/inc/cordebug.idl @@ -3813,6 +3813,7 @@ interface ICorDebugRegisterSet : IUnknown REGISTER_ARM_D30, REGISTER_ARM_D31, + // ARM64 registers REGISTER_ARM64_PC = 0, diff --git a/src/coreclr/src/pal/prebuilt/inc/cordebug.h b/src/coreclr/src/pal/prebuilt/inc/cordebug.h index 59375ba..f633fda 100644 --- a/src/coreclr/src/pal/prebuilt/inc/cordebug.h +++ b/src/coreclr/src/pal/prebuilt/inc/cordebug.h @@ -8851,6 +8851,38 @@ enum CorDebugRegister REGISTER_ARM_R11 = ( REGISTER_ARM_R10 + 1 ) , REGISTER_ARM_R12 = ( REGISTER_ARM_R11 + 1 ) , REGISTER_ARM_LR = ( REGISTER_ARM_R12 + 1 ) , + REGISTER_ARM_D0 = ( REGISTER_ARM_LR + 1 ) , + REGISTER_ARM_D1 = ( REGISTER_ARM_D0 + 1 ) , + REGISTER_ARM_D2 = ( REGISTER_ARM_D1 + 1 ) , + REGISTER_ARM_D3 = ( REGISTER_ARM_D2 + 1 ) , + REGISTER_ARM_D4 = ( REGISTER_ARM_D3 + 1 ) , + REGISTER_ARM_D5 = ( REGISTER_ARM_D4 + 1 ) , + REGISTER_ARM_D6 = ( REGISTER_ARM_D5 + 1 ) , + REGISTER_ARM_D7 = ( REGISTER_ARM_D6 + 1 ) , + REGISTER_ARM_D8 = ( REGISTER_ARM_D7 + 1 ) , + REGISTER_ARM_D9 = ( REGISTER_ARM_D8 + 1 ) , + REGISTER_ARM_D10 = ( REGISTER_ARM_D9 + 1 ) , + REGISTER_ARM_D11 = ( REGISTER_ARM_D10 + 1 ) , + REGISTER_ARM_D12 = ( REGISTER_ARM_D11 + 1 ) , + REGISTER_ARM_D13 = ( REGISTER_ARM_D12 + 1 ) , + REGISTER_ARM_D14 = ( REGISTER_ARM_D13 + 1 ) , + REGISTER_ARM_D15 = ( REGISTER_ARM_D14 + 1 ) , + REGISTER_ARM_D16 = ( REGISTER_ARM_D15 + 1 ) , + REGISTER_ARM_D17 = ( REGISTER_ARM_D16 + 1 ) , + REGISTER_ARM_D18 = ( REGISTER_ARM_D17 + 1 ) , + REGISTER_ARM_D19 = ( REGISTER_ARM_D18 + 1 ) , + REGISTER_ARM_D20 = ( REGISTER_ARM_D19 + 1 ) , + REGISTER_ARM_D21 = ( REGISTER_ARM_D20 + 1 ) , + REGISTER_ARM_D22 = ( REGISTER_ARM_D21 + 1 ) , + REGISTER_ARM_D23 = ( REGISTER_ARM_D22 + 1 ) , + REGISTER_ARM_D24 = ( REGISTER_ARM_D23 + 1 ) , + REGISTER_ARM_D25 = ( REGISTER_ARM_D24 + 1 ) , + REGISTER_ARM_D26 = ( REGISTER_ARM_D25 + 1 ) , + REGISTER_ARM_D27 = ( REGISTER_ARM_D26 + 1 ) , + REGISTER_ARM_D28 = ( REGISTER_ARM_D27 + 1 ) , + REGISTER_ARM_D29 = ( REGISTER_ARM_D28 + 1 ) , + REGISTER_ARM_D30 = ( REGISTER_ARM_D29 + 1 ) , + REGISTER_ARM_D31 = ( REGISTER_ARM_D30 + 1 ) , REGISTER_ARM64_PC = 0, REGISTER_ARM64_SP = ( REGISTER_ARM64_PC + 1 ) , REGISTER_ARM64_FP = ( REGISTER_ARM64_SP + 1 ) , -- 2.7.4