From 982aa9170e82283f379dfefe9959c97b5c08bcb1 Mon Sep 17 00:00:00 2001 From: yroux Date: Mon, 12 Jan 2015 14:07:05 +0000 Subject: [PATCH] gcc/testsuite/ 2015-01-12 Yvan Roux Backport from trunk r211075. 2014-04-30 Alan Lawrence gcc.target/arm/simd/vrev16p8_1.c: New file. gcc.target/arm/simd/vrev16qp8_1.c: New file. gcc.target/arm/simd/vrev16qs8_1.c: New file. gcc.target/arm/simd/vrev16qu8_1.c: New file. gcc.target/arm/simd/vrev16s8_1.c: New file. gcc.target/arm/simd/vrev16u8_1.c: New file. gcc.target/arm/simd/vrev32p16_1.c: New file. gcc.target/arm/simd/vrev32p8_1.c: New file. gcc.target/arm/simd/vrev32qp16_1.c: New file. gcc.target/arm/simd/vrev32qp8_1.c: New file. gcc.target/arm/simd/vrev32qs16_1.c: New file. gcc.target/arm/simd/vrev32qs8_1.c: New file. gcc.target/arm/simd/vrev32qu16_1.c: New file. gcc.target/arm/simd/vrev32qu8_1.c: New file. gcc.target/arm/simd/vrev32s16_1.c: New file. gcc.target/arm/simd/vrev32s8_1.c: New file. gcc.target/arm/simd/vrev32u16_1.c: New file. gcc.target/arm/simd/vrev32u8_1.c: New file. gcc.target/arm/simd/vrev64f32_1.c: New file. gcc.target/arm/simd/vrev64p16_1.c: New file. gcc.target/arm/simd/vrev64p8_1.c: New file. gcc.target/arm/simd/vrev64qf32_1.c: New file. gcc.target/arm/simd/vrev64qp16_1.c: New file. gcc.target/arm/simd/vrev64qp8_1.c: New file. gcc.target/arm/simd/vrev64qs16_1.c: New file. gcc.target/arm/simd/vrev64qs32_1.c: New file. gcc.target/arm/simd/vrev64qs8_1.c: New file. gcc.target/arm/simd/vrev64qu16_1.c: New file. gcc.target/arm/simd/vrev64qu32_1.c: New file. gcc.target/arm/simd/vrev64qu8_1.c: New file. gcc.target/arm/simd/vrev64s16_1.c: New file. gcc.target/arm/simd/vrev64s32_1.c: New file. gcc.target/arm/simd/vrev64s8_1.c: New file. gcc.target/arm/simd/vrev64u16_1.c: New file. gcc.target/arm/simd/vrev64u32_1.c: New file. gcc.target/arm/simd/vrev64u8_1.c: New file. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@219465 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/testsuite/ChangeLog.linaro | 42 ++++++++++++++++++++++++ gcc/testsuite/gcc.target/arm/simd/vrev16p8_1.c | 12 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev16qp8_1.c | 12 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev16qs8_1.c | 12 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev16qu8_1.c | 12 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev16s8_1.c | 12 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev16u8_1.c | 12 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev32p16_1.c | 12 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev32p8_1.c | 12 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev32qp16_1.c | 12 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev32qp8_1.c | 12 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev32qs16_1.c | 12 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev32qs8_1.c | 12 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev32qu16_1.c | 12 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev32qu8_1.c | 12 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev32s16_1.c | 12 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev32s8_1.c | 12 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev32u16_1.c | 12 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev32u8_1.c | 12 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev64f32_1.c | 12 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev64p16_1.c | 12 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev64p8_1.c | 12 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev64qf32_1.c | 12 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev64qp16_1.c | 12 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev64qp8_1.c | 12 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev64qs16_1.c | 12 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev64qs32_1.c | 12 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev64qs8_1.c | 12 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev64qu16_1.c | 12 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev64qu32_1.c | 12 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev64qu8_1.c | 12 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev64s16_1.c | 12 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev64s32_1.c | 12 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev64s8_1.c | 12 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev64u16_1.c | 12 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev64u32_1.c | 12 +++++++ gcc/testsuite/gcc.target/arm/simd/vrev64u8_1.c | 12 +++++++ 37 files changed, 474 insertions(+) create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev16p8_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev16qp8_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev16qs8_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev16qu8_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev16s8_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev16u8_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev32p16_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev32p8_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev32qp16_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev32qp8_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev32qs16_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev32qs8_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev32qu16_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev32qu8_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev32s16_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev32s8_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev32u16_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev32u8_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev64f32_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev64p16_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev64p8_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev64qf32_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev64qp16_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev64qp8_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev64qs16_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev64qs32_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev64qs8_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev64qu16_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev64qu32_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev64qu8_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev64s16_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev64s32_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev64s8_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev64u16_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev64u32_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vrev64u8_1.c diff --git a/gcc/testsuite/ChangeLog.linaro b/gcc/testsuite/ChangeLog.linaro index e492e79..973b7aef 100644 --- a/gcc/testsuite/ChangeLog.linaro +++ b/gcc/testsuite/ChangeLog.linaro @@ -1,3 +1,45 @@ +2015-01-12 Yvan Roux + + Backport from trunk r211075. + 2014-04-30 Alan Lawrence + + gcc.target/arm/simd/vrev16p8_1.c: New file. + gcc.target/arm/simd/vrev16qp8_1.c: New file. + gcc.target/arm/simd/vrev16qs8_1.c: New file. + gcc.target/arm/simd/vrev16qu8_1.c: New file. + gcc.target/arm/simd/vrev16s8_1.c: New file. + gcc.target/arm/simd/vrev16u8_1.c: New file. + gcc.target/arm/simd/vrev32p16_1.c: New file. + gcc.target/arm/simd/vrev32p8_1.c: New file. + gcc.target/arm/simd/vrev32qp16_1.c: New file. + gcc.target/arm/simd/vrev32qp8_1.c: New file. + gcc.target/arm/simd/vrev32qs16_1.c: New file. + gcc.target/arm/simd/vrev32qs8_1.c: New file. + gcc.target/arm/simd/vrev32qu16_1.c: New file. + gcc.target/arm/simd/vrev32qu8_1.c: New file. + gcc.target/arm/simd/vrev32s16_1.c: New file. + gcc.target/arm/simd/vrev32s8_1.c: New file. + gcc.target/arm/simd/vrev32u16_1.c: New file. + gcc.target/arm/simd/vrev32u8_1.c: New file. + gcc.target/arm/simd/vrev64f32_1.c: New file. + gcc.target/arm/simd/vrev64p16_1.c: New file. + gcc.target/arm/simd/vrev64p8_1.c: New file. + gcc.target/arm/simd/vrev64qf32_1.c: New file. + gcc.target/arm/simd/vrev64qp16_1.c: New file. + gcc.target/arm/simd/vrev64qp8_1.c: New file. + gcc.target/arm/simd/vrev64qs16_1.c: New file. + gcc.target/arm/simd/vrev64qs32_1.c: New file. + gcc.target/arm/simd/vrev64qs8_1.c: New file. + gcc.target/arm/simd/vrev64qu16_1.c: New file. + gcc.target/arm/simd/vrev64qu32_1.c: New file. + gcc.target/arm/simd/vrev64qu8_1.c: New file. + gcc.target/arm/simd/vrev64s16_1.c: New file. + gcc.target/arm/simd/vrev64s32_1.c: New file. + gcc.target/arm/simd/vrev64s8_1.c: New file. + gcc.target/arm/simd/vrev64u16_1.c: New file. + gcc.target/arm/simd/vrev64u32_1.c: New file. + gcc.target/arm/simd/vrev64u8_1.c: New file. + 2015-01-11 Yvan Roux Backport from trunk r209620. diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev16p8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev16p8_1.c new file mode 100644 index 0000000..fddb32f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev16p8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev16p8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev16p8.x" + +/* { dg-final { scan-assembler "vrev16\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev16qp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev16qp8_1.c new file mode 100644 index 0000000..b4634b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev16qp8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev16q_p8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev16qp8.x" + +/* { dg-final { scan-assembler "vrev16\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev16qs8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev16qs8_1.c new file mode 100644 index 0000000..691799b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev16qs8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev16q_s8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev16qs8.x" + +/* { dg-final { scan-assembler "vrev16\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev16qu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev16qu8_1.c new file mode 100644 index 0000000..f6ab4ac --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev16qu8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev16q_u8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev16qu8.x" + +/* { dg-final { scan-assembler "vrev16\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev16s8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev16s8_1.c new file mode 100644 index 0000000..0a03721 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev16s8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev16s8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev16s8.x" + +/* { dg-final { scan-assembler "vrev16\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev16u8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev16u8_1.c new file mode 100644 index 0000000..7e5f548 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev16u8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev16u8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev16u8.x" + +/* { dg-final { scan-assembler "vrev16\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32p16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32p16_1.c new file mode 100644 index 0000000..f3643fa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev32p16_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev32p16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev32p16.x" + +/* { dg-final { scan-assembler "vrev32\.16\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32p8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32p8_1.c new file mode 100644 index 0000000..d823e59 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev32p8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev32p8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev32p8.x" + +/* { dg-final { scan-assembler "vrev32\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32qp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32qp16_1.c new file mode 100644 index 0000000..f8ba8a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev32qp16_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev32q_p16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev32qp16.x" + +/* { dg-final { scan-assembler "vrev32\.16\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32qp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32qp8_1.c new file mode 100644 index 0000000..0ddf608 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev32qp8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev32q_p8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev32qp8.x" + +/* { dg-final { scan-assembler "vrev32\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32qs16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32qs16_1.c new file mode 100644 index 0000000..30d0314 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev32qs16_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev32q_s16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev32qs16.x" + +/* { dg-final { scan-assembler "vrev32\.16\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32qs8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32qs8_1.c new file mode 100644 index 0000000..03ddd2b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev32qs8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev32q_s8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev32qs8.x" + +/* { dg-final { scan-assembler "vrev32\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32qu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32qu16_1.c new file mode 100644 index 0000000..7176543 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev32qu16_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev32q_u16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev32qu16.x" + +/* { dg-final { scan-assembler "vrev32\.16\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32qu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32qu8_1.c new file mode 100644 index 0000000..403292c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev32qu8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev32q_u8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev32qu8.x" + +/* { dg-final { scan-assembler "vrev32\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32s16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32s16_1.c new file mode 100644 index 0000000..e182ab9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev32s16_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev32s16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev32s16.x" + +/* { dg-final { scan-assembler "vrev32\.16\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32s8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32s8_1.c new file mode 100644 index 0000000..a48c415 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev32s8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev32s8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev32s8.x" + +/* { dg-final { scan-assembler "vrev32\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32u16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32u16_1.c new file mode 100644 index 0000000..076f8ab --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev32u16_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev32u16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev32u16.x" + +/* { dg-final { scan-assembler "vrev32\.16\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32u8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32u8_1.c new file mode 100644 index 0000000..240d459 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev32u8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev32u8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev32u8.x" + +/* { dg-final { scan-assembler "vrev32\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64f32_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64f32_1.c new file mode 100644 index 0000000..f5d3bca --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64f32_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64f32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64f32.x" + +/* { dg-final { scan-assembler "vrev64\.32\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64p16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64p16_1.c new file mode 100644 index 0000000..8c685c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64p16_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64p16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64p16.x" + +/* { dg-final { scan-assembler "vrev64\.16\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64p8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64p8_1.c new file mode 100644 index 0000000..67ac1e4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64p8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64p8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64p8.x" + +/* { dg-final { scan-assembler "vrev64\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qf32_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qf32_1.c new file mode 100644 index 0000000..74130b7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qf32_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64q_f32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64qf32.x" + +/* { dg-final { scan-assembler "vrev64\.32\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qp16_1.c new file mode 100644 index 0000000..71f3b4b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qp16_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64q_p16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64qp16.x" + +/* { dg-final { scan-assembler "vrev64\.16\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qp8_1.c new file mode 100644 index 0000000..324a738 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qp8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64q_p8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64qp8.x" + +/* { dg-final { scan-assembler "vrev64\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qs16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qs16_1.c new file mode 100644 index 0000000..9a373ec --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qs16_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64q_s16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64qs16.x" + +/* { dg-final { scan-assembler "vrev64\.16\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qs32_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qs32_1.c new file mode 100644 index 0000000..0f10c6c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qs32_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64q_s32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64qs32.x" + +/* { dg-final { scan-assembler "vrev64\.32\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qs8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qs8_1.c new file mode 100644 index 0000000..cf38014 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qs8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64q_s8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64qs8.x" + +/* { dg-final { scan-assembler "vrev64\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qu16_1.c new file mode 100644 index 0000000..010d6db --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qu16_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64q_u16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64qu16.x" + +/* { dg-final { scan-assembler "vrev64\.16\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qu32_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qu32_1.c new file mode 100644 index 0000000..908769c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qu32_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64q_u32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64qu32.x" + +/* { dg-final { scan-assembler "vrev64\.32\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qu8_1.c new file mode 100644 index 0000000..2fa07d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qu8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64q_u8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64qu8.x" + +/* { dg-final { scan-assembler "vrev64\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64s16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64s16_1.c new file mode 100644 index 0000000..f14319c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64s16_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64s16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64s16.x" + +/* { dg-final { scan-assembler "vrev64\.16\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64s32_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64s32_1.c new file mode 100644 index 0000000..ead5722 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64s32_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64s32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64s32.x" + +/* { dg-final { scan-assembler "vrev64\.32\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64s8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64s8_1.c new file mode 100644 index 0000000..29d684d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64s8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64s8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64s8.x" + +/* { dg-final { scan-assembler "vrev64\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64u16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64u16_1.c new file mode 100644 index 0000000..feddacc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64u16_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64u16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64u16.x" + +/* { dg-final { scan-assembler "vrev64\.16\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64u32_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64u32_1.c new file mode 100644 index 0000000..92a81f4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64u32_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64u32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64u32.x" + +/* { dg-final { scan-assembler "vrev64\.32\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64u8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64u8_1.c new file mode 100644 index 0000000..f904af5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64u8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64u8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64u8.x" + +/* { dg-final { scan-assembler "vrev64\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ -- 2.7.4