From 980c4df037649b375f952f4ee786582c6c8eb750 Mon Sep 17 00:00:00 2001 From: Reid Kleckner Date: Mon, 23 Jul 2018 21:14:35 +0000 Subject: [PATCH] Re-land r335297 "[X86] Implement more of x86-64 large and medium PIC code models" Don't try to generate large PIC code for non-ELF targets. Neither COFF nor MachO have relocations for large position independent code, and users have been using "large PIC" code models to JIT 64-bit code for a while now. With this change, if they are generating ELF code, their JITed code will truly be PIC, but if they target MachO or COFF, it will contain 64-bit immediates that directly reference external symbols. For a JIT, that's perfectly fine. llvm-svn: 337740 --- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 10 +- llvm/lib/Target/X86/X86InstrCompiler.td | 4 + llvm/lib/Target/X86/X86InstrInfo.cpp | 60 +++- llvm/lib/Target/X86/X86MCInstLower.cpp | 35 ++ llvm/lib/Target/X86/X86Subtarget.cpp | 44 ++- llvm/lib/Target/X86/X86TargetMachine.cpp | 8 +- .../test/CodeGen/X86/cleanuppad-large-codemodel.ll | 2 +- llvm/test/CodeGen/X86/code-model-elf.ll | 384 +++++++++++++++++++++ llvm/test/CodeGen/X86/fast-isel-call-cleanup.ll | 4 +- llvm/test/CodeGen/X86/hipe-cc64.ll | 2 +- llvm/test/CodeGen/X86/variadic-node-pic.ll | 6 +- llvm/test/ExecutionEngine/MCJIT/eh-lg-pic.ll | 6 + llvm/test/ExecutionEngine/OrcMCJIT/eh-lg-pic.ll | 6 + llvm/utils/UpdateTestChecks/asm.py | 5 +- llvm/utils/update_llc_test_checks.py | 5 + 15 files changed, 545 insertions(+), 36 deletions(-) create mode 100644 llvm/test/CodeGen/X86/code-model-elf.ll diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp index f42e626..a28d4ea 100644 --- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -991,11 +991,13 @@ bool X86DAGToDAGISel::matchWrapper(SDValue N, X86ISelAddressMode &AM) { bool IsRIPRel = N.getOpcode() == X86ISD::WrapperRIP; - // Only do this address mode folding for 64-bit if we're in the small code - // model. - // FIXME: But we can do GOTPCREL addressing in the medium code model. + // We can't use an addressing mode in the 64-bit large code model. In the + // medium code model, we use can use an mode when RIP wrappers are present. + // That signifies access to globals that are known to be "near", such as the + // GOT itself. CodeModel::Model M = TM.getCodeModel(); - if (Subtarget->is64Bit() && M != CodeModel::Small && M != CodeModel::Kernel) + if (Subtarget->is64Bit() && + (M == CodeModel::Large || (M == CodeModel::Medium && !IsRIPRel))) return true; // Base and index reg must be 0 in order to use %rip as base. diff --git a/llvm/lib/Target/X86/X86InstrCompiler.td b/llvm/lib/Target/X86/X86InstrCompiler.td index f360c0a..373f850 100644 --- a/llvm/lib/Target/X86/X86InstrCompiler.td +++ b/llvm/lib/Target/X86/X86InstrCompiler.td @@ -37,6 +37,10 @@ let hasSideEffects = 0, isNotDuplicable = 1, Uses = [ESP, SSP], def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label), "", []>; +// 64-bit large code model PIC base construction. +let hasSideEffects = 0, mayLoad = 1, isNotDuplicable = 1, SchedRW = [WriteJump] in + def MOVGOT64r : PseudoI<(outs GR64:$reg), + (ins GR64:$scratch, i64i32imm_pcrel:$got), []>; // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into // a stack adjustment and the codegen must know that they may modify the stack diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index ee0a6e2..c5d10fc 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -5851,7 +5851,9 @@ isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { /// TODO: Eliminate this and move the code to X86MachineFunctionInfo. /// unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const { - assert(!Subtarget.is64Bit() && + assert((!Subtarget.is64Bit() || + MF->getTarget().getCodeModel() == CodeModel::Medium || + MF->getTarget().getCodeModel() == CodeModel::Large) && "X86-64 PIC uses RIP relative addressing"); X86MachineFunctionInfo *X86FI = MF->getInfo(); @@ -5862,7 +5864,8 @@ unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const { // Create the register. The code to initialize it is inserted // later, by the CGBR pass (below). MachineRegisterInfo &RegInfo = MF->getRegInfo(); - GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass); + GlobalBaseReg = RegInfo.createVirtualRegister( + Subtarget.is64Bit() ? &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass); X86FI->setGlobalBaseReg(GlobalBaseReg); return GlobalBaseReg; } @@ -7321,9 +7324,10 @@ namespace { static_cast(&MF.getTarget()); const X86Subtarget &STI = MF.getSubtarget(); - // Don't do anything if this is 64-bit as 64-bit PIC - // uses RIP relative addressing. - if (STI.is64Bit()) + // Don't do anything in the 64-bit small and kernel code models. They use + // RIP-relative addressing for everything. + if (STI.is64Bit() && (TM->getCodeModel() == CodeModel::Small || + TM->getCodeModel() == CodeModel::Kernel)) return false; // Only emit a global base reg in PIC mode. @@ -7350,17 +7354,41 @@ namespace { else PC = GlobalBaseReg; - // Operand of MovePCtoStack is completely ignored by asm printer. It's - // only used in JIT code emission as displacement to pc. - BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0); - - // If we're using vanilla 'GOT' PIC style, we should use relative addressing - // not to pc, but to _GLOBAL_OFFSET_TABLE_ external. - if (STI.isPICStyleGOT()) { - // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register - BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg) - .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_", - X86II::MO_GOT_ABSOLUTE_ADDRESS); + if (STI.is64Bit()) { + if (TM->getCodeModel() == CodeModel::Medium) { + // In the medium code model, use a RIP-relative LEA to materialize the + // GOT. + BuildMI(FirstMBB, MBBI, DL, TII->get(X86::LEA64r), PC) + .addReg(X86::RIP) + .addImm(0) + .addReg(0) + .addExternalSymbol("_GLOBAL_OFFSET_TABLE_") + .addReg(0); + } else if (TM->getCodeModel() == CodeModel::Large) { + // Loading the GOT in the large code model requires math with labels, + // so we use a pseudo instruction and expand it during MC emission. + unsigned Scratch = RegInfo.createVirtualRegister(&X86::GR64RegClass); + BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVGOT64r), PC) + .addReg(Scratch, RegState::Undef | RegState::Define) + .addExternalSymbol("_GLOBAL_OFFSET_TABLE_"); + } else { + llvm_unreachable("unexpected code model"); + } + } else { + // Operand of MovePCtoStack is completely ignored by asm printer. It's + // only used in JIT code emission as displacement to pc. + BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0); + + // If we're using vanilla 'GOT' PIC style, we should use relative + // addressing not to pc, but to _GLOBAL_OFFSET_TABLE_ external. + if (STI.isPICStyleGOT()) { + // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], + // %some_register + BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg) + .addReg(PC) + .addExternalSymbol("_GLOBAL_OFFSET_TABLE_", + X86II::MO_GOT_ABSOLUTE_ADDRESS); + } } return true; diff --git a/llvm/lib/Target/X86/X86MCInstLower.cpp b/llvm/lib/Target/X86/X86MCInstLower.cpp index 9ca5de6..d38c7b4 100644 --- a/llvm/lib/Target/X86/X86MCInstLower.cpp +++ b/llvm/lib/Target/X86/X86MCInstLower.cpp @@ -1720,6 +1720,41 @@ void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) { return; } + case X86::MOVGOT64r: { + // Materializes the GOT for the 64-bit large code model. + MCSymbol *DotSym = OutContext.createTempSymbol(); + OutStreamer->EmitLabel(DotSym); + + unsigned DstReg = MI->getOperand(0).getReg(); + unsigned ScratchReg = MI->getOperand(1).getReg(); + MCSymbol *GOTSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2)); + + // .LtmpN: leaq .LtmpN(%rip), %dst + const MCExpr *DotExpr = MCSymbolRefExpr::create(DotSym, OutContext); + EmitAndCountInstruction(MCInstBuilder(X86::LEA64r) + .addReg(DstReg) // dest + .addReg(X86::RIP) // base + .addImm(1) // scale + .addReg(0) // index + .addExpr(DotExpr) // disp + .addReg(0)); // seg + + // movq $_GLOBAL_OFFSET_TABLE_ - .LtmpN, %scratch + const MCExpr *GOTSymExpr = MCSymbolRefExpr::create(GOTSym, OutContext); + const MCExpr *GOTDiffExpr = + MCBinaryExpr::createSub(GOTSymExpr, DotExpr, OutContext); + EmitAndCountInstruction(MCInstBuilder(X86::MOV64ri) + .addReg(ScratchReg) // dest + .addExpr(GOTDiffExpr)); // disp + + // addq %scratch, %dst + EmitAndCountInstruction(MCInstBuilder(X86::ADD64rr) + .addReg(DstReg) // dest + .addReg(DstReg) // dest + .addReg(ScratchReg)); // src + return; + } + case X86::ADD32ri: { // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri. if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS) diff --git a/llvm/lib/Target/X86/X86Subtarget.cpp b/llvm/lib/Target/X86/X86Subtarget.cpp index 8e1e35e..7e84323 100644 --- a/llvm/lib/Target/X86/X86Subtarget.cpp +++ b/llvm/lib/Target/X86/X86Subtarget.cpp @@ -68,14 +68,36 @@ X86Subtarget::classifyGlobalReference(const GlobalValue *GV) const { unsigned char X86Subtarget::classifyLocalReference(const GlobalValue *GV) const { - // 64 bits can use %rip addressing for anything local. - if (is64Bit()) + // If we're not PIC, it's not very interesting. + if (!isPositionIndependent()) return X86II::MO_NO_FLAG; - // If this is for a position dependent executable, the static linker can - // figure it out. - if (!isPositionIndependent()) + if (is64Bit()) { + // 64-bit ELF PIC local references may use GOTOFF relocations. + if (isTargetELF()) { + switch (TM.getCodeModel()) { + // 64-bit small code model is simple: All rip-relative. + case CodeModel::Small: + case CodeModel::Kernel: + return X86II::MO_NO_FLAG; + + // The large PIC code model uses GOTOFF. + case CodeModel::Large: + return X86II::MO_GOTOFF; + + // Medium is a hybrid: RIP-rel for code, GOTOFF for DSO local data. + case CodeModel::Medium: + if (isa(GV)) + return X86II::MO_NO_FLAG; // All code is RIP-relative + return X86II::MO_GOTOFF; // Local symbols use GOTOFF. + } + llvm_unreachable("invalid code model"); + } + + // Otherwise, this is either a RIP-relative reference or a 64-bit movabsq, + // both of which use MO_NO_FLAG. return X86II::MO_NO_FLAG; + } // The COFF dynamic linker just patches the executable sections. if (isTargetCOFF()) @@ -97,8 +119,8 @@ X86Subtarget::classifyLocalReference(const GlobalValue *GV) const { unsigned char X86Subtarget::classifyGlobalReference(const GlobalValue *GV, const Module &M) const { - // Large model never uses stubs. - if (TM.getCodeModel() == CodeModel::Large) + // The static large model never uses stubs. + if (TM.getCodeModel() == CodeModel::Large && !isPositionIndependent()) return X86II::MO_NO_FLAG; // Absolute symbols can be referenced directly. @@ -120,8 +142,14 @@ unsigned char X86Subtarget::classifyGlobalReference(const GlobalValue *GV, if (isTargetCOFF()) return X86II::MO_DLLIMPORT; - if (is64Bit()) + if (is64Bit()) { + // ELF supports a large, truly PIC code model with non-PC relative GOT + // references. Other object file formats do not. Use the no-flag, 64-bit + // reference for them. + if (TM.getCodeModel() == CodeModel::Large) + return isTargetELF() ? X86II::MO_GOT : X86II::MO_NO_FLAG; return X86II::MO_GOTPCREL; + } if (isTargetDarwin()) { if (!isPositionIndependent()) diff --git a/llvm/lib/Target/X86/X86TargetMachine.cpp b/llvm/lib/Target/X86/X86TargetMachine.cpp index b76e8c2..374bf3d 100644 --- a/llvm/lib/Target/X86/X86TargetMachine.cpp +++ b/llvm/lib/Target/X86/X86TargetMachine.cpp @@ -160,9 +160,15 @@ static std::string computeDataLayout(const Triple &TT) { } static Reloc::Model getEffectiveRelocModel(const Triple &TT, + bool JIT, Optional RM) { bool is64Bit = TT.getArch() == Triple::x86_64; if (!RM.hasValue()) { + // JIT codegen should use static relocations by default, since it's + // typically executed in process and not relocatable. + if (JIT) + return Reloc::Static; + // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode. // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we // use static relocation model by default. @@ -214,7 +220,7 @@ X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT, CodeGenOpt::Level OL, bool JIT) : LLVMTargetMachine( T, computeDataLayout(TT), TT, CPU, FS, Options, - getEffectiveRelocModel(TT, RM), + getEffectiveRelocModel(TT, JIT, RM), getEffectiveCodeModel(CM, JIT, TT.getArch() == Triple::x86_64), OL), TLOF(createTLOF(getTargetTriple())) { // Windows stack unwinder gets confused when execution flow "falls through" diff --git a/llvm/test/CodeGen/X86/cleanuppad-large-codemodel.ll b/llvm/test/CodeGen/X86/cleanuppad-large-codemodel.ll index 8ffb97d..55911e3 100644 --- a/llvm/test/CodeGen/X86/cleanuppad-large-codemodel.ll +++ b/llvm/test/CodeGen/X86/cleanuppad-large-codemodel.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=x86_64-pc-windows-msvc -code-model=large -o - < %s | FileCheck %s +; RUN: llc -mtriple=x86_64-pc-windows-msvc -code-model=large -relocation-model=static -o - < %s | FileCheck %s declare i32 @__CxxFrameHandler3(...) diff --git a/llvm/test/CodeGen/X86/code-model-elf.ll b/llvm/test/CodeGen/X86/code-model-elf.ll new file mode 100644 index 0000000..6d62f25 --- /dev/null +++ b/llvm/test/CodeGen/X86/code-model-elf.ll @@ -0,0 +1,384 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; Run with --no_x86_scrub_rip because we care a lot about how globals are +; accessed in the code model. + +; RUN: llc < %s -relocation-model=static -code-model=small | FileCheck %s --check-prefix=CHECK --check-prefix=SMALL-STATIC +; RUN: llc < %s -relocation-model=static -code-model=medium | FileCheck %s --check-prefix=CHECK --check-prefix=MEDIUM-STATIC +; RUN: llc < %s -relocation-model=static -code-model=large | FileCheck %s --check-prefix=CHECK --check-prefix=LARGE-STATIC +; RUN: llc < %s -relocation-model=pic -code-model=small | FileCheck %s --check-prefix=CHECK --check-prefix=SMALL-PIC +; RUN: llc < %s -relocation-model=pic -code-model=medium | FileCheck %s --check-prefix=CHECK --check-prefix=MEDIUM-PIC +; RUN: llc < %s -relocation-model=pic -code-model=large | FileCheck %s --check-prefix=CHECK --check-prefix=LARGE-PIC + +; Generated from this C source: +; +; static int static_data[10]; +; int global_data[10] = {1, 2}; +; extern int extern_data[10]; +; +; int *lea_static_data() { return &static_data[0]; } +; int *lea_global_data() { return &global_data[0]; } +; int *lea_extern_data() { return &extern_data[0]; } +; +; static void static_fn(void) {} +; void global_fn(void) {} +; void extern_fn(void); +; +; typedef void (*void_fn)(void); +; void_fn lea_static_fn() { return &static_fn; } +; void_fn lea_global_fn() { return &global_fn; } +; void_fn lea_extern_fn() { return &extern_fn; } + + +; ModuleID = 'model.c' +source_filename = "model.c" +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64--linux" + +@global_data = dso_local global [10 x i32] [i32 1, i32 2, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0], align 16 +@static_data = internal global [10 x i32] zeroinitializer, align 16 +@extern_data = external global [10 x i32], align 16 + +define dso_local i32* @lea_static_data() #0 { +; SMALL-STATIC-LABEL: lea_static_data: +; SMALL-STATIC: # %bb.0: +; SMALL-STATIC-NEXT: movl $static_data, %eax +; SMALL-STATIC-NEXT: retq +; +; MEDIUM-STATIC-LABEL: lea_static_data: +; MEDIUM-STATIC: # %bb.0: +; MEDIUM-STATIC-NEXT: movabsq $static_data, %rax +; MEDIUM-STATIC-NEXT: retq +; +; LARGE-STATIC-LABEL: lea_static_data: +; LARGE-STATIC: # %bb.0: +; LARGE-STATIC-NEXT: movabsq $static_data, %rax +; LARGE-STATIC-NEXT: retq +; +; SMALL-PIC-LABEL: lea_static_data: +; SMALL-PIC: # %bb.0: +; SMALL-PIC-NEXT: leaq static_data(%rip), %rax +; SMALL-PIC-NEXT: retq +; +; MEDIUM-PIC-LABEL: lea_static_data: +; MEDIUM-PIC: # %bb.0: +; MEDIUM-PIC-NEXT: leaq _GLOBAL_OFFSET_TABLE_(%rip), %rcx +; MEDIUM-PIC-NEXT: movabsq $static_data@GOTOFF, %rax +; MEDIUM-PIC-NEXT: addq %rcx, %rax +; MEDIUM-PIC-NEXT: retq +; +; LARGE-PIC-LABEL: lea_static_data: +; LARGE-PIC: # %bb.0: +; LARGE-PIC-NEXT: .Ltmp0: +; LARGE-PIC-NEXT: leaq .Ltmp0(%rip), %rcx +; LARGE-PIC-NEXT: movabsq $_GLOBAL_OFFSET_TABLE_-.Ltmp0, %rax +; LARGE-PIC-NEXT: addq %rax, %rcx +; LARGE-PIC-NEXT: movabsq $static_data@GOTOFF, %rax +; LARGE-PIC-NEXT: addq %rcx, %rax +; LARGE-PIC-NEXT: retq + ret i32* getelementptr inbounds ([10 x i32], [10 x i32]* @static_data, i64 0, i64 0) +} + +define dso_local i32* @lea_global_data() #0 { +; SMALL-STATIC-LABEL: lea_global_data: +; SMALL-STATIC: # %bb.0: +; SMALL-STATIC-NEXT: movl $global_data, %eax +; SMALL-STATIC-NEXT: retq +; +; MEDIUM-STATIC-LABEL: lea_global_data: +; MEDIUM-STATIC: # %bb.0: +; MEDIUM-STATIC-NEXT: movabsq $global_data, %rax +; MEDIUM-STATIC-NEXT: retq +; +; LARGE-STATIC-LABEL: lea_global_data: +; LARGE-STATIC: # %bb.0: +; LARGE-STATIC-NEXT: movabsq $global_data, %rax +; LARGE-STATIC-NEXT: retq +; +; SMALL-PIC-LABEL: lea_global_data: +; SMALL-PIC: # %bb.0: +; SMALL-PIC-NEXT: leaq global_data(%rip), %rax +; SMALL-PIC-NEXT: retq +; +; MEDIUM-PIC-LABEL: lea_global_data: +; MEDIUM-PIC: # %bb.0: +; MEDIUM-PIC-NEXT: leaq _GLOBAL_OFFSET_TABLE_(%rip), %rcx +; MEDIUM-PIC-NEXT: movabsq $global_data@GOTOFF, %rax +; MEDIUM-PIC-NEXT: addq %rcx, %rax +; MEDIUM-PIC-NEXT: retq +; +; LARGE-PIC-LABEL: lea_global_data: +; LARGE-PIC: # %bb.0: +; LARGE-PIC-NEXT: .Ltmp1: +; LARGE-PIC-NEXT: leaq .Ltmp1(%rip), %rcx +; LARGE-PIC-NEXT: movabsq $_GLOBAL_OFFSET_TABLE_-.Ltmp1, %rax +; LARGE-PIC-NEXT: addq %rax, %rcx +; LARGE-PIC-NEXT: movabsq $global_data@GOTOFF, %rax +; LARGE-PIC-NEXT: addq %rcx, %rax +; LARGE-PIC-NEXT: retq + ret i32* getelementptr inbounds ([10 x i32], [10 x i32]* @global_data, i64 0, i64 0) +} + +define dso_local i32* @lea_extern_data() #0 { +; SMALL-STATIC-LABEL: lea_extern_data: +; SMALL-STATIC: # %bb.0: +; SMALL-STATIC-NEXT: movl $extern_data, %eax +; SMALL-STATIC-NEXT: retq +; +; MEDIUM-STATIC-LABEL: lea_extern_data: +; MEDIUM-STATIC: # %bb.0: +; MEDIUM-STATIC-NEXT: movabsq $extern_data, %rax +; MEDIUM-STATIC-NEXT: retq +; +; LARGE-STATIC-LABEL: lea_extern_data: +; LARGE-STATIC: # %bb.0: +; LARGE-STATIC-NEXT: movabsq $extern_data, %rax +; LARGE-STATIC-NEXT: retq +; +; SMALL-PIC-LABEL: lea_extern_data: +; SMALL-PIC: # %bb.0: +; SMALL-PIC-NEXT: movq extern_data@GOTPCREL(%rip), %rax +; SMALL-PIC-NEXT: retq +; +; MEDIUM-PIC-LABEL: lea_extern_data: +; MEDIUM-PIC: # %bb.0: +; MEDIUM-PIC-NEXT: movq extern_data@GOTPCREL(%rip), %rax +; MEDIUM-PIC-NEXT: retq +; +; LARGE-PIC-LABEL: lea_extern_data: +; LARGE-PIC: # %bb.0: +; LARGE-PIC-NEXT: .Ltmp2: +; LARGE-PIC-NEXT: leaq .Ltmp2(%rip), %rax +; LARGE-PIC-NEXT: movabsq $_GLOBAL_OFFSET_TABLE_-.Ltmp2, %rcx +; LARGE-PIC-NEXT: addq %rcx, %rax +; LARGE-PIC-NEXT: movabsq $extern_data@GOT, %rcx +; LARGE-PIC-NEXT: movq (%rax,%rcx), %rax +; LARGE-PIC-NEXT: retq + ret i32* getelementptr inbounds ([10 x i32], [10 x i32]* @extern_data, i64 0, i64 0) +} + +define dso_local i32 @load_global_data() #0 { +; SMALL-STATIC-LABEL: load_global_data: +; SMALL-STATIC: # %bb.0: +; SMALL-STATIC-NEXT: movl global_data+8(%rip), %eax +; SMALL-STATIC-NEXT: retq +; +; MEDIUM-STATIC-LABEL: load_global_data: +; MEDIUM-STATIC: # %bb.0: +; MEDIUM-STATIC-NEXT: movabsq $global_data, %rax +; MEDIUM-STATIC-NEXT: movl 8(%rax), %eax +; MEDIUM-STATIC-NEXT: retq +; +; LARGE-STATIC-LABEL: load_global_data: +; LARGE-STATIC: # %bb.0: +; LARGE-STATIC-NEXT: movabsq $global_data, %rax +; LARGE-STATIC-NEXT: movl 8(%rax), %eax +; LARGE-STATIC-NEXT: retq +; +; SMALL-PIC-LABEL: load_global_data: +; SMALL-PIC: # %bb.0: +; SMALL-PIC-NEXT: movl global_data+8(%rip), %eax +; SMALL-PIC-NEXT: retq +; +; MEDIUM-PIC-LABEL: load_global_data: +; MEDIUM-PIC: # %bb.0: +; MEDIUM-PIC-NEXT: leaq _GLOBAL_OFFSET_TABLE_(%rip), %rax +; MEDIUM-PIC-NEXT: movabsq $global_data@GOTOFF, %rcx +; MEDIUM-PIC-NEXT: movl 8(%rax,%rcx), %eax +; MEDIUM-PIC-NEXT: retq +; +; LARGE-PIC-LABEL: load_global_data: +; LARGE-PIC: # %bb.0: +; LARGE-PIC-NEXT: .Ltmp3: +; LARGE-PIC-NEXT: leaq .Ltmp3(%rip), %rax +; LARGE-PIC-NEXT: movabsq $_GLOBAL_OFFSET_TABLE_-.Ltmp3, %rcx +; LARGE-PIC-NEXT: addq %rcx, %rax +; LARGE-PIC-NEXT: movabsq $global_data@GOTOFF, %rcx +; LARGE-PIC-NEXT: movl 8(%rax,%rcx), %eax +; LARGE-PIC-NEXT: retq + %rv = load i32, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @global_data, i64 0, i64 2) + ret i32 %rv +} + +define dso_local i32 @load_extern_data() #0 { +; SMALL-STATIC-LABEL: load_extern_data: +; SMALL-STATIC: # %bb.0: +; SMALL-STATIC-NEXT: movl extern_data+8(%rip), %eax +; SMALL-STATIC-NEXT: retq +; +; MEDIUM-STATIC-LABEL: load_extern_data: +; MEDIUM-STATIC: # %bb.0: +; MEDIUM-STATIC-NEXT: movabsq $extern_data, %rax +; MEDIUM-STATIC-NEXT: movl 8(%rax), %eax +; MEDIUM-STATIC-NEXT: retq +; +; LARGE-STATIC-LABEL: load_extern_data: +; LARGE-STATIC: # %bb.0: +; LARGE-STATIC-NEXT: movabsq $extern_data, %rax +; LARGE-STATIC-NEXT: movl 8(%rax), %eax +; LARGE-STATIC-NEXT: retq +; +; SMALL-PIC-LABEL: load_extern_data: +; SMALL-PIC: # %bb.0: +; SMALL-PIC-NEXT: movq extern_data@GOTPCREL(%rip), %rax +; SMALL-PIC-NEXT: movl 8(%rax), %eax +; SMALL-PIC-NEXT: retq +; +; MEDIUM-PIC-LABEL: load_extern_data: +; MEDIUM-PIC: # %bb.0: +; MEDIUM-PIC-NEXT: movq extern_data@GOTPCREL(%rip), %rax +; MEDIUM-PIC-NEXT: movl 8(%rax), %eax +; MEDIUM-PIC-NEXT: retq +; +; LARGE-PIC-LABEL: load_extern_data: +; LARGE-PIC: # %bb.0: +; LARGE-PIC-NEXT: .Ltmp4: +; LARGE-PIC-NEXT: leaq .Ltmp4(%rip), %rax +; LARGE-PIC-NEXT: movabsq $_GLOBAL_OFFSET_TABLE_-.Ltmp4, %rcx +; LARGE-PIC-NEXT: addq %rcx, %rax +; LARGE-PIC-NEXT: movabsq $extern_data@GOT, %rcx +; LARGE-PIC-NEXT: movq (%rax,%rcx), %rax +; LARGE-PIC-NEXT: movl 8(%rax), %eax +; LARGE-PIC-NEXT: retq + %rv = load i32, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @extern_data, i64 0, i64 2) + ret i32 %rv +} + +define dso_local void @global_fn() #0 { +; CHECK-LABEL: global_fn: +; CHECK: # %bb.0: +; CHECK-NEXT: retq + ret void +} + +define internal void @static_fn() #0 { +; CHECK-LABEL: static_fn: +; CHECK: # %bb.0: +; CHECK-NEXT: retq + ret void +} + +declare void @extern_fn() + +define dso_local void ()* @lea_static_fn() #0 { +; SMALL-STATIC-LABEL: lea_static_fn: +; SMALL-STATIC: # %bb.0: +; SMALL-STATIC-NEXT: movl $static_fn, %eax +; SMALL-STATIC-NEXT: retq +; +; MEDIUM-STATIC-LABEL: lea_static_fn: +; MEDIUM-STATIC: # %bb.0: +; MEDIUM-STATIC-NEXT: movabsq $static_fn, %rax +; MEDIUM-STATIC-NEXT: retq +; +; LARGE-STATIC-LABEL: lea_static_fn: +; LARGE-STATIC: # %bb.0: +; LARGE-STATIC-NEXT: movabsq $static_fn, %rax +; LARGE-STATIC-NEXT: retq +; +; SMALL-PIC-LABEL: lea_static_fn: +; SMALL-PIC: # %bb.0: +; SMALL-PIC-NEXT: leaq static_fn(%rip), %rax +; SMALL-PIC-NEXT: retq +; +; MEDIUM-PIC-LABEL: lea_static_fn: +; MEDIUM-PIC: # %bb.0: +; MEDIUM-PIC-NEXT: movabsq $static_fn, %rax +; MEDIUM-PIC-NEXT: retq +; +; LARGE-PIC-LABEL: lea_static_fn: +; LARGE-PIC: # %bb.0: +; LARGE-PIC-NEXT: .Ltmp5: +; LARGE-PIC-NEXT: leaq .Ltmp5(%rip), %rcx +; LARGE-PIC-NEXT: movabsq $_GLOBAL_OFFSET_TABLE_-.Ltmp5, %rax +; LARGE-PIC-NEXT: addq %rax, %rcx +; LARGE-PIC-NEXT: movabsq $static_fn@GOTOFF, %rax +; LARGE-PIC-NEXT: addq %rcx, %rax +; LARGE-PIC-NEXT: retq + ret void ()* @static_fn +} + +define dso_local void ()* @lea_global_fn() #0 { +; SMALL-STATIC-LABEL: lea_global_fn: +; SMALL-STATIC: # %bb.0: +; SMALL-STATIC-NEXT: movl $global_fn, %eax +; SMALL-STATIC-NEXT: retq +; +; MEDIUM-STATIC-LABEL: lea_global_fn: +; MEDIUM-STATIC: # %bb.0: +; MEDIUM-STATIC-NEXT: movabsq $global_fn, %rax +; MEDIUM-STATIC-NEXT: retq +; +; LARGE-STATIC-LABEL: lea_global_fn: +; LARGE-STATIC: # %bb.0: +; LARGE-STATIC-NEXT: movabsq $global_fn, %rax +; LARGE-STATIC-NEXT: retq +; +; SMALL-PIC-LABEL: lea_global_fn: +; SMALL-PIC: # %bb.0: +; SMALL-PIC-NEXT: leaq global_fn(%rip), %rax +; SMALL-PIC-NEXT: retq +; +; MEDIUM-PIC-LABEL: lea_global_fn: +; MEDIUM-PIC: # %bb.0: +; MEDIUM-PIC-NEXT: movabsq $global_fn, %rax +; MEDIUM-PIC-NEXT: retq +; +; LARGE-PIC-LABEL: lea_global_fn: +; LARGE-PIC: # %bb.0: +; LARGE-PIC-NEXT: .Ltmp6: +; LARGE-PIC-NEXT: leaq .Ltmp6(%rip), %rcx +; LARGE-PIC-NEXT: movabsq $_GLOBAL_OFFSET_TABLE_-.Ltmp6, %rax +; LARGE-PIC-NEXT: addq %rax, %rcx +; LARGE-PIC-NEXT: movabsq $global_fn@GOTOFF, %rax +; LARGE-PIC-NEXT: addq %rcx, %rax +; LARGE-PIC-NEXT: retq + ret void ()* @global_fn +} + +define dso_local void ()* @lea_extern_fn() #0 { +; SMALL-STATIC-LABEL: lea_extern_fn: +; SMALL-STATIC: # %bb.0: +; SMALL-STATIC-NEXT: movl $extern_fn, %eax +; SMALL-STATIC-NEXT: retq +; +; MEDIUM-STATIC-LABEL: lea_extern_fn: +; MEDIUM-STATIC: # %bb.0: +; MEDIUM-STATIC-NEXT: movabsq $extern_fn, %rax +; MEDIUM-STATIC-NEXT: retq +; +; LARGE-STATIC-LABEL: lea_extern_fn: +; LARGE-STATIC: # %bb.0: +; LARGE-STATIC-NEXT: movabsq $extern_fn, %rax +; LARGE-STATIC-NEXT: retq +; +; SMALL-PIC-LABEL: lea_extern_fn: +; SMALL-PIC: # %bb.0: +; SMALL-PIC-NEXT: movq extern_fn@GOTPCREL(%rip), %rax +; SMALL-PIC-NEXT: retq +; +; MEDIUM-PIC-LABEL: lea_extern_fn: +; MEDIUM-PIC: # %bb.0: +; MEDIUM-PIC-NEXT: movq extern_fn@GOTPCREL(%rip), %rax +; MEDIUM-PIC-NEXT: retq +; +; LARGE-PIC-LABEL: lea_extern_fn: +; LARGE-PIC: # %bb.0: +; LARGE-PIC-NEXT: .Ltmp7: +; LARGE-PIC-NEXT: leaq .Ltmp7(%rip), %rax +; LARGE-PIC-NEXT: movabsq $_GLOBAL_OFFSET_TABLE_-.Ltmp7, %rcx +; LARGE-PIC-NEXT: addq %rcx, %rax +; LARGE-PIC-NEXT: movabsq $extern_fn@GOT, %rcx +; LARGE-PIC-NEXT: movq (%rax,%rcx), %rax +; LARGE-PIC-NEXT: retq + ret void ()* @extern_fn +} + +attributes #0 = { noinline nounwind uwtable } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 7, !"PIC Level", i32 2} +!2 = !{i32 7, !"PIE Level", i32 2} +!3 = !{!"clang version 7.0.0 "} diff --git a/llvm/test/CodeGen/X86/fast-isel-call-cleanup.ll b/llvm/test/CodeGen/X86/fast-isel-call-cleanup.ll index 27e4241..1f7a59e 100644 --- a/llvm/test/CodeGen/X86/fast-isel-call-cleanup.ll +++ b/llvm/test/CodeGen/X86/fast-isel-call-cleanup.ll @@ -1,4 +1,4 @@ -; RUN: llc -fast-isel-sink-local-values -fast-isel -O0 -code-model=large -mcpu=generic -mtriple=x86_64-apple-darwin10 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -fast-isel-sink-local-values -fast-isel -O0 -code-model=large -mcpu=generic -mtriple=x86_64-linux -relocation-model=static < %s | FileCheck %s ; Check that fast-isel cleans up when it fails to lower a call instruction. define void @fastiselcall() { @@ -9,7 +9,7 @@ entry: ; FastISel's local value code was dead, so it's gone. ; CHECK-NOT: movl $42, ; SDag-ISel's arg mov: -; CHECK: movabsq $_targetfn, %[[REG:[^ ]*]] +; CHECK: movabsq $targetfn, %[[REG:[^ ]*]] ; CHECK: movl $42, %edi ; CHECK: callq *%[[REG]] diff --git a/llvm/test/CodeGen/X86/hipe-cc64.ll b/llvm/test/CodeGen/X86/hipe-cc64.ll index ce2d0e9..cf5788f 100644 --- a/llvm/test/CodeGen/X86/hipe-cc64.ll +++ b/llvm/test/CodeGen/X86/hipe-cc64.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -stack-symbol-ordering=0 -tailcallopt -code-model=medium -stack-alignment=8 -mtriple=x86_64-linux-gnu -mcpu=opteron | FileCheck %s +; RUN: llc < %s -stack-symbol-ordering=0 -tailcallopt -relocation-model=static -code-model=medium -stack-alignment=8 -mtriple=x86_64-linux-gnu -mcpu=opteron | FileCheck %s ; Check the HiPE calling convention works (x86-64) diff --git a/llvm/test/CodeGen/X86/variadic-node-pic.ll b/llvm/test/CodeGen/X86/variadic-node-pic.ll index 704459e6..0d4287d 100644 --- a/llvm/test/CodeGen/X86/variadic-node-pic.ll +++ b/llvm/test/CodeGen/X86/variadic-node-pic.ll @@ -1,4 +1,8 @@ -; RUN: llc < %s -relocation-model=pic -code-model=large +; RUN: llc < %s -relocation-model=pic -code-model=large | FileCheck %s + +; CHECK-LABEL: foo: +; CHECK: movabsq $_xscanf, %[[REG:[^ ]*]] +; CHECK: callq *%[[REG]] target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" target triple = "x86_64-apple-darwin8" diff --git a/llvm/test/ExecutionEngine/MCJIT/eh-lg-pic.ll b/llvm/test/ExecutionEngine/MCJIT/eh-lg-pic.ll index b5b9d54..8d41fe6 100644 --- a/llvm/test/ExecutionEngine/MCJIT/eh-lg-pic.ll +++ b/llvm/test/ExecutionEngine/MCJIT/eh-lg-pic.ll @@ -15,8 +15,14 @@ define void @throwException() { unreachable } +; Make an internal function so we exercise R_X86_64_GOTOFF64 relocations. +define internal dso_local void @use_gotoff() { + ret void +} + define i32 @main() personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { entry: + call void @use_gotoff() invoke void @throwException() to label %try.cont unwind label %lpad diff --git a/llvm/test/ExecutionEngine/OrcMCJIT/eh-lg-pic.ll b/llvm/test/ExecutionEngine/OrcMCJIT/eh-lg-pic.ll index 809f68f..ce927c0 100644 --- a/llvm/test/ExecutionEngine/OrcMCJIT/eh-lg-pic.ll +++ b/llvm/test/ExecutionEngine/OrcMCJIT/eh-lg-pic.ll @@ -15,8 +15,14 @@ define void @throwException() { unreachable } +; Make an internal function so we exercise R_X86_64_GOTOFF64 relocations. +define internal dso_local void @use_gotoff() { + ret void +} + define i32 @main() personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { entry: + call void @use_gotoff() invoke void @throwException() to label %try.cont unwind label %lpad diff --git a/llvm/utils/UpdateTestChecks/asm.py b/llvm/utils/UpdateTestChecks/asm.py index e3f1489..726a653 100644 --- a/llvm/utils/UpdateTestChecks/asm.py +++ b/llvm/utils/UpdateTestChecks/asm.py @@ -110,8 +110,9 @@ def scrub_asm_x86(asm, args): asm = SCRUB_X86_SPILL_RELOAD_RE.sub(r'{{[-0-9]+}}(%\1{{[sb]}}p)\2', asm) # Generically match the stack offset of a memory operand. asm = SCRUB_X86_SP_RE.sub(r'{{[0-9]+}}(%\1)', asm) - # Generically match a RIP-relative memory operand. - asm = SCRUB_X86_RIP_RE.sub(r'{{.*}}(%rip)', asm) + if getattr(args, 'x86_scrub_rip', False): + # Generically match a RIP-relative memory operand. + asm = SCRUB_X86_RIP_RE.sub(r'{{.*}}(%rip)', asm) # Generically match a LCP symbol. asm = SCRUB_X86_LCP_RE.sub(r'{{\.LCPI.*}}', asm) if getattr(args, 'extra_scrub', False): diff --git a/llvm/utils/update_llc_test_checks.py b/llvm/utils/update_llc_test_checks.py index f7d94cd..09b49a7 100755 --- a/llvm/utils/update_llc_test_checks.py +++ b/llvm/utils/update_llc_test_checks.py @@ -30,6 +30,11 @@ def main(): parser.add_argument( '--extra_scrub', action='store_true', help='Always use additional regex to further reduce diffs between various subtargets') + parser.add_argument( + '--x86_scrub_rip', action='store_true', default=True, + help='Use more regex for x86 matching to reduce diffs between various subtargets') + parser.add_argument( + '--no_x86_scrub_rip', action='store_false', dest='x86_scrub_rip') parser.add_argument('tests', nargs='+') args = parser.parse_args() -- 2.7.4