From 97b5fb78d137a44bec104ba073dd620008ed7abb Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Sat, 25 Jul 2020 16:58:15 -0400 Subject: [PATCH] GlobalISel: Translate llvm.convert.{to|from}.fp16 intrinsics I think these were added as a workaround for SelectionDAG lacking half legalization support in the past. I think they should probably be removed from the IR, but clang does still have a target control to emit these instead of the native half fpext/fptrunc. --- llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 12 +++++++++ .../irtranslator-convert-fp16-intrinsics.ll | 31 ++++++++++++++++++++++ 2 files changed, 43 insertions(+) create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-convert-fp16-intrinsics.ll diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp index 6433c13..dba3416 100644 --- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -1543,6 +1543,18 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID, } return true; } + case Intrinsic::convert_from_fp16: + // FIXME: This intrinsic should probably be removed from the IR. + MIRBuilder.buildFPExt(getOrCreateVReg(CI), + getOrCreateVReg(*CI.getArgOperand(0)), + MachineInstr::copyFlagsFromInstruction(CI)); + return true; + case Intrinsic::convert_to_fp16: + // FIXME: This intrinsic should probably be removed from the IR. + MIRBuilder.buildFPTrunc(getOrCreateVReg(CI), + getOrCreateVReg(*CI.getArgOperand(0)), + MachineInstr::copyFlagsFromInstruction(CI)); + return true; case Intrinsic::memcpy: case Intrinsic::memmove: case Intrinsic::memset: diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-convert-fp16-intrinsics.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-convert-fp16-intrinsics.ll new file mode 100644 index 0000000..065a3d8 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-convert-fp16-intrinsics.ll @@ -0,0 +1,31 @@ +; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +; RUN: llc -mtriple=aarch64-- -mcpu=falkor -mattr=+lse -O0 -aarch64-enable-atomic-cfg-tidy=0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - | FileCheck %s + +define i16 @convert_to_fp16(float %src) { + ; CHECK-LABEL: name: convert_to_fp16 + ; CHECK: bb.1 (%ir-block.0): + ; CHECK: liveins: $s0 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $s0 + ; CHECK: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY]](s32) + ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16) + ; CHECK: $w0 = COPY [[ANYEXT]](s32) + ; CHECK: RET_ReallyLR implicit $w0 + %cvt = call i16 @llvm.convert.to.fp16.f32(float %src) + ret i16 %cvt +} + +define float @convert_from_fp16(i16 %src) { + ; CHECK-LABEL: name: convert_from_fp16 + ; CHECK: bb.1 (%ir-block.0): + ; CHECK: liveins: $w0 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 + ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) + ; CHECK: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16) + ; CHECK: $s0 = COPY [[FPEXT]](s32) + ; CHECK: RET_ReallyLR implicit $s0 + %cvt = call float @llvm.convert.from.fp16.f32(i16 %src) + ret float %cvt +} + +declare i16 @llvm.convert.to.fp16.f32(float) nounwind readnone +declare float @llvm.convert.from.fp16.f32(i16) nounwind readnone -- 2.7.4