From 9786e7552d5564268484357866088d0a054bccaf Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Tue, 26 May 2020 12:58:18 -0400 Subject: [PATCH] Revert "[AMDGPU] NFC target dependent requiresUniformRegister refactored out" This reverts commit fb38b98338cc87442e3451665e82bf1c8ef9388f. This will regress compile time. --- llvm/include/llvm/CodeGen/TargetLowering.h | 13 ++++++------- llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp | 3 ++- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 6 ------ llvm/lib/Target/AMDGPU/SIISelLowering.h | 5 ++--- 4 files changed, 10 insertions(+), 17 deletions(-) diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h index 70bc6b9..2689838 100644 --- a/llvm/include/llvm/CodeGen/TargetLowering.h +++ b/llvm/include/llvm/CodeGen/TargetLowering.h @@ -28,7 +28,6 @@ #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringRef.h" -#include "llvm/Analysis/LegacyDivergenceAnalysis.h" #include "llvm/CodeGen/DAGCombine.h" #include "llvm/CodeGen/ISDOpcodes.h" #include "llvm/CodeGen/RuntimeLibcalls.h" @@ -822,12 +821,12 @@ public: return RC; } - /// Allows target to decide about the divergence of the - /// specific value. Base class implementation returns true - /// if the Divergece Analysis exists and reports value as divergent. - virtual bool isDivergent(const LegacyDivergenceAnalysis *DA, - MachineFunction &MF, const Value *V) const { - return DA && DA->isDivergent(V); + /// Allows target to decide about the register class of the + /// specific value that is live outside the defining block. + /// Returns true if the value needs uniform register class. + virtual bool requiresUniformRegister(MachineFunction &MF, + const Value *) const { + return false; } /// Return the 'representative' register class for the specified value diff --git a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp index 36e9ea5..7a5fd7d 100644 --- a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp @@ -398,7 +398,8 @@ Register FunctionLoweringInfo::CreateRegs(Type *Ty, bool isDivergent) { } Register FunctionLoweringInfo::CreateRegs(const Value *V) { - return CreateRegs(V->getType(), TLI->isDivergent(DA, *MF, V)); + return CreateRegs(V->getType(), DA && DA->isDivergent(V) && + !TLI->requiresUniformRegister(*MF, V)); } /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 722275e..2c147fa 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -11226,12 +11226,6 @@ SITargetLowering::getRegClassFor(MVT VT, bool isDivergent) const { return RC; } -bool SITargetLowering::isDivergent(const LegacyDivergenceAnalysis *DA, - MachineFunction &MF, const Value *V) const { - return !requiresUniformRegister(MF, V) && - TargetLoweringBase::isDivergent(DA, MF, V); -} - // FIXME: This is a workaround for DivergenceAnalysis not understanding always // uniform values (as produced by the mask results of control flow intrinsics) // used outside of divergent blocks. The phi users need to also be treated as diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.h b/llvm/lib/Target/AMDGPU/SIISelLowering.h index 80f3a87c..7ef11eb 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.h +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.h @@ -416,9 +416,8 @@ public: virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent) const override; - virtual bool isDivergent(const LegacyDivergenceAnalysis *DA, - MachineFunction &MF, const Value *V) const override; - bool requiresUniformRegister(MachineFunction &MF, const Value *V) const; + virtual bool requiresUniformRegister(MachineFunction &MF, + const Value *V) const override; Align getPrefLoopAlignment(MachineLoop *ML) const override; void allocateHSAUserSGPRs(CCState &CCInfo, -- 2.7.4