From 975c0eeb31e6cdc0d48f28d3ba9b2e36ccc0726e Mon Sep 17 00:00:00 2001 From: Yong Qin Date: Mon, 18 Mar 2019 17:20:09 +0800 Subject: [PATCH] di: exit play local 4k video flashing [1/1] PD#SWPL-5877 Problem: 1.afbc mode, play h.265 local video, when exit playing, screen will flashing sometimes. 2.when exit playing, there cost 5s time. Solution: 4k video di bypass, afbc hw module used by vpp, when DI unreg, needn't to disable AFBC moudule. Verify: tl1 Change-Id: I2ac66a145a009042d286dda50e7259657f4bfc8e Signed-off-by: Yong Qin --- drivers/amlogic/media/deinterlace/deinterlace.c | 43 ++++++---------------- drivers/amlogic/media/deinterlace/deinterlace_hw.c | 35 +++++++++--------- 2 files changed, 30 insertions(+), 48 deletions(-) diff --git a/drivers/amlogic/media/deinterlace/deinterlace.c b/drivers/amlogic/media/deinterlace/deinterlace.c index ce72f8b..0aeacb8 100644 --- a/drivers/amlogic/media/deinterlace/deinterlace.c +++ b/drivers/amlogic/media/deinterlace/deinterlace.c @@ -129,7 +129,7 @@ static di_dev_t *de_devp; static dev_t di_devno; static struct class *di_clsp; -static const char version_s[] = "2019-03-18a"; +static const char version_s[] = "2019-03-19"; static int bypass_state = 1; static int bypass_all; @@ -274,8 +274,8 @@ static int di_receiver_event_fun(int type, void *data, void *arg); static void di_uninit_buf(unsigned int disable_mirror); static void log_buffer_state(unsigned char *tag); /* static void put_get_disp_buf(void); */ -static unsigned int isbypass_flag; -static unsigned int needbypass_flag; +static unsigned int isbypass_flag = true; +static unsigned int needbypass_flag = true; static const struct vframe_receiver_op_s di_vf_receiver = { @@ -6010,8 +6010,15 @@ static void di_unreg_process_irq(void) #endif adpative_combing_exit(); enable_di_pre_mif(false, mcpre_en); - afbc_reg_sw(false); - afbc_input_sw(false); + /*disable afbc module when afbc working in DI*/ + #if 0 + if (IS_COMP_MODE(di_pre_stru.cur_inp_type) && + (!needbypass_flag && !isbypass_flag)) { + pr_info("DI: disable afbc\n"); + afbc_reg_sw(false); + afbc_input_sw(false); + } + #endif di_hw_uninit(); if (is_meson_txlx_cpu() || is_meson_txhd_cpu() || is_meson_g12a_cpu() || is_meson_g12b_cpu() @@ -6667,19 +6674,6 @@ static int di_receiver_event_fun(int type, void *data, void *arg) di_pre_stru.reg_req_flag, di_pre_stru.reg_req_flag_irq); di_pre_stru.vdin_source = false; - - /*check reg process, and waiting reg*/ - di_pre_stru.unreg_req_flag_cnt = 0; - while (di_pre_stru.reg_req_flag || - di_pre_stru.reg_req_flag_irq) { - msleep(20); - if (di_pre_stru.unreg_req_flag_cnt++ > - di_reg_unreg_cnt) { - pr_err("DI : reg to unreg timeout!!!\n"); - di_reg_process(); - break; - } - } di_pre_stru.unreg_req_flag = 1; trigger_pre_di_process(TRIGGER_PRE_BY_PROVERDER_UNREG); /*check unreg process*/ @@ -6900,19 +6894,6 @@ light_unreg: di_pre_stru.unreg_req_flag_irq); trigger_pre_di_process(TRIGGER_PRE_BY_PROVERDER_REG); - /*check unreg process*/ - di_pre_stru.reg_req_flag_cnt = 0; - while (di_pre_stru.unreg_req_flag || - di_pre_stru.unreg_req_flag_irq) { - msleep(20); - if (di_pre_stru.reg_req_flag_cnt++ > di_reg_unreg_cnt) { - pr_err("%s:unreg to reg timeout!!!\n", - __func__); - di_unreg_process(); - break; - } - } - di_pre_stru.reg_req_flag = 1; /*check reg process*/ di_pre_stru.reg_req_flag_cnt = 0; diff --git a/drivers/amlogic/media/deinterlace/deinterlace_hw.c b/drivers/amlogic/media/deinterlace/deinterlace_hw.c index 5e5dd4c..407b2bb 100644 --- a/drivers/amlogic/media/deinterlace/deinterlace_hw.c +++ b/drivers/amlogic/media/deinterlace/deinterlace_hw.c @@ -1140,7 +1140,7 @@ u32 enable_afbc_input(struct vframe_s *vf) return true; } - +#if 0 static void afbcx_power_sw(enum eAFBC_DEC decsel, bool on) /*g12a*/ { unsigned int reg_ctrl; @@ -1155,23 +1155,23 @@ static void afbcx_power_sw(enum eAFBC_DEC decsel, bool on) /*g12a*/ RDMA_WR_BITS(reg_ctrl, 0x55, 0, 8); } - +#endif static void afbcx_sw(bool on) /*g12a*/ { unsigned int tmp; unsigned int mask; unsigned int reg_ctrl, reg_en; enum eAFBC_DEC dec_sel; + const unsigned int *reg = afbc_get_regbase(); dec_sel = afbc_get_decnub(); if (dec_sel == eAFBC_DEC0) { reg_ctrl = VD1_AFBCD0_MISC_CTRL; - reg_en = AFBC_ENABLE; } else { reg_ctrl = VD2_AFBCD1_MISC_CTRL; - reg_en = VD2_AFBC_ENABLE; } + reg_en = reg[eAFBC_ENABLE]; mask = (3<<20) | (1<<12) | (1<<9); /*clear*/ @@ -1198,24 +1198,15 @@ static void afbcx_sw(bool on) /*g12a*/ if (is_meson_tl1_cpu()) RDMA_WR_BITS(VD1_AFBCD0_MISC_CTRL, 0, 22, 1); } -// printk("%s,on[%d],CTRL[0x%x],en[0x%x]\n", __func__, on, -// RDMA_RD(VD1_AFBCD0_MISC_CTRL), -// RDMA_RD(VD1_AFBCD0_MISC_CTRL)); } static void afbc_sw_old(bool on)/*txlx*/ { enum eAFBC_DEC dec_sel; unsigned int reg_en; + const unsigned int *reg = afbc_get_regbase(); dec_sel = afbc_get_decnub(); - - if (dec_sel == eAFBC_DEC0) { - //reg_ctrl = VD1_AFBCD0_MISC_CTRL; - reg_en = AFBC_ENABLE; - } else { - //reg_ctrl = VD2_AFBCD1_MISC_CTRL; - reg_en = VD2_AFBC_ENABLE; - } + reg_en = reg[eAFBC_ENABLE]; if (on) { /* DI inp(current data) switch to AFBC */ @@ -1257,6 +1248,7 @@ static void afbc_power_sw(bool on) /*afbc*/ enum eAFBC_DEC dec_sel; unsigned int vpu_sel; + unsigned int reg_ctrl; dec_sel = afbc_get_decnub(); if (dec_sel == eAFBC_DEC0) @@ -1267,8 +1259,17 @@ static void afbc_power_sw(bool on) switch_vpu_mem_pd_vmod(vpu_sel, on?VPU_MEM_POWER_ON:VPU_MEM_POWER_DOWN); - if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) - afbcx_power_sw(dec_sel, on); + if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) { + if (dec_sel == eAFBC_DEC0) + reg_ctrl = VD1_AFBCD0_MISC_CTRL; + else + reg_ctrl = VD2_AFBCD1_MISC_CTRL; + if (on) + RDMA_WR_BITS(reg_ctrl, 0, 0, 8); + else + RDMA_WR_BITS(reg_ctrl, 0x55, 0, 8); + } + /*afbcx_power_sw(dec_sel, on);*/ } static int afbc_reg_unreg_flag; -- 2.7.4