From 96913bbf3eba74e2bf509fe7196be073eaf2ea60 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Fri, 28 Oct 2022 08:29:47 -0400 Subject: [PATCH] ac/surface: force linear image layout for chips not supporting image opcodes Image opcodes will be emulated. Reviewed-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/amd/common/ac_gpu_info.c | 3 +++ src/amd/common/ac_gpu_info.h | 1 + src/amd/common/ac_surface.c | 4 ++++ src/amd/vulkan/winsys/null/radv_null_winsys.c | 1 + 4 files changed, 9 insertions(+) diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index 7fdaa8e..470225a 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -1340,6 +1340,8 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info) } info->has_3d_cube_border_color_mipmap = info->has_graphics || info->family == CHIP_MI100; + info->has_image_opcodes = debug_get_bool_option("AMD_IMAGE_OPCODES", + info->has_graphics || info->family < CHIP_GFX940); info->never_stop_sq_perf_counters = info->gfx_level == GFX10 || info->gfx_level == GFX10_3; info->never_send_perfcounter_stop = info->gfx_level == GFX11; @@ -1612,6 +1614,7 @@ void ac_print_gpu_info(struct radeon_info *info, FILE *f) fprintf(f, " has_ls_vgpr_init_bug = %i\n", info->has_ls_vgpr_init_bug); fprintf(f, " has_32bit_predication = %i\n", info->has_32bit_predication); fprintf(f, " has_3d_cube_border_color_mipmap = %i\n", info->has_3d_cube_border_color_mipmap); + fprintf(f, " has_image_opcodes = %i\n", info->has_image_opcodes); fprintf(f, " never_stop_sq_perf_counters = %i\n", info->never_stop_sq_perf_counters); fprintf(f, " has_sqtt_rb_harvest_bug = %i\n", info->has_sqtt_rb_harvest_bug); fprintf(f, " has_sqtt_auto_flush_mode_bug = %i\n", info->has_sqtt_auto_flush_mode_bug); diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index b21a3a3..119db53 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -121,6 +121,7 @@ struct radeon_info { bool has_cs_regalloc_hang_bug; bool has_32bit_predication; bool has_3d_cube_border_color_mipmap; + bool has_image_opcodes; bool never_stop_sq_perf_counters; bool has_sqtt_rb_harvest_bug; bool has_sqtt_auto_flush_mode_bug; diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index 783b854..024013d 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -2515,6 +2515,10 @@ int ac_compute_surface(struct ac_addrlib *addrlib, const struct radeon_info *inf if (r) return r; + /* Images are emulated on some CDNA chips. */ + if (!info->has_image_opcodes) + mode = RADEON_SURF_MODE_LINEAR_ALIGNED; + if (info->family_id >= FAMILY_AI) r = gfx9_compute_surface(addrlib, info, config, mode, surf); else diff --git a/src/amd/vulkan/winsys/null/radv_null_winsys.c b/src/amd/vulkan/winsys/null/radv_null_winsys.c index c89b745..28864a4 100644 --- a/src/amd/vulkan/winsys/null/radv_null_winsys.c +++ b/src/amd/vulkan/winsys/null/radv_null_winsys.c @@ -128,6 +128,7 @@ radv_null_winsys_query_info(struct radeon_winsys *rws, struct radeon_info *info) info->num_physical_sgprs_per_simd = 512; info->has_3d_cube_border_color_mipmap = true; + info->has_image_opcodes = true; if (info->family == CHIP_GFX1100 || info->family == CHIP_GFX1101) info->num_physical_wave64_vgprs_per_simd = 768; -- 2.7.4