From 9665f98c106e4ce1abfc21b4c1d1139b8d43341b Mon Sep 17 00:00:00 2001 From: Colin LeMahieu Date: Fri, 5 Dec 2014 21:09:27 +0000 Subject: [PATCH] [Hexagon] Updating mux_ir/ri/ii/rr with encoding bits llvm-svn: 223515 --- llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp | 6 +- llvm/lib/Target/Hexagon/HexagonInstrInfo.td | 102 +++++++++++++++-------- llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td | 6 +- llvm/lib/Target/Hexagon/HexagonPeephole.cpp | 10 +-- llvm/test/MC/Disassembler/Hexagon/alu32_perm.txt | 8 ++ 5 files changed, 86 insertions(+), 46 deletions(-) diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp index c59bc0b..59fd7c6 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -343,15 +343,15 @@ static unsigned doesIntrinsicContainPredicate(unsigned ID) // Mapping hexagon_C2_muxir to MUX_pri. This is pretty weird - but // that's how it's mapped in q6protos.h. case Intrinsic::hexagon_C2_muxir: - return Hexagon::MUX_ri; + return Hexagon::C2_muxri; // Mapping hexagon_C2_muxri to MUX_pir. This is pretty weird - but // that's how it's mapped in q6protos.h. case Intrinsic::hexagon_C2_muxri: - return Hexagon::MUX_ir; + return Hexagon::C2_muxir; case Intrinsic::hexagon_C2_muxii: - return Hexagon::MUX_ii; + return Hexagon::C2_muxii; case Intrinsic::hexagon_C2_vmux: return Hexagon::VMUX_prr64; case Intrinsic::hexagon_S2_valignrb: diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td index 08d1d6c..8f70ace 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td @@ -248,7 +248,8 @@ def: T_cmp32_rr_pat; def: T_cmp32_rr_pat, i1>; def: T_cmp32_rr_pat, i1>; -let CextOpcode = "MUX", InputType = "reg", hasNewValue = 1 in +let CextOpcode = "MUX", InputType = "reg", hasNewValue = 1, + isCodeGenOnly = 0 in def C2_mux: ALU32_rr<(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt), "$Rd = mux($Pu, $Rs, $Rt)", [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel { @@ -737,6 +738,63 @@ def TFCR : CRInst<(outs CRRegs:$dst), (ins IntRegs:$src1), // ALU32/PERM + //===----------------------------------------------------------------------===// +// Scalar mux register immediate. +let hasSideEffects = 0, isExtentSigned = 1, CextOpcode = "MUX", + InputType = "imm", hasNewValue = 1, isExtendable = 1, opExtentBits = 8 in +class T_MUX1 + : ALU32Inst <(outs IntRegs:$Rd), ins, AsmStr>, ImmRegRel { + bits<5> Rd; + bits<2> Pu; + bits<8> s8; + bits<5> Rs; + + let IClass = 0b0111; + let Inst{27-24} = 0b0011; + let Inst{23} = MajOp; + let Inst{22-21} = Pu; + let Inst{20-16} = Rs; + let Inst{13} = 0b0; + let Inst{12-5} = s8; + let Inst{4-0} = Rd; +} + +let opExtendable = 2, isCodeGenOnly = 0 in +def C2_muxri : T_MUX1<0b1, (ins PredRegs:$Pu, s8Ext:$s8, IntRegs:$Rs), + "$Rd = mux($Pu, #$s8, $Rs)">; + +let opExtendable = 3, isCodeGenOnly = 0 in +def C2_muxir : T_MUX1<0b0, (ins PredRegs:$Pu, IntRegs:$Rs, s8Ext:$s8), + "$Rd = mux($Pu, $Rs, #$s8)">; + +def : Pat<(i32 (select I1:$Pu, s8ExtPred:$s8, I32:$Rs)), + (C2_muxri I1:$Pu, s8ExtPred:$s8, I32:$Rs)>; + +def : Pat<(i32 (select I1:$Pu, I32:$Rs, s8ExtPred:$s8)), + (C2_muxir I1:$Pu, I32:$Rs, s8ExtPred:$s8)>; + +// C2_muxii: Scalar mux immediates. +let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1, + opExtentBits = 8, opExtendable = 2, isCodeGenOnly = 0 in +def C2_muxii: ALU32Inst <(outs IntRegs:$Rd), + (ins PredRegs:$Pu, s8Ext:$s8, s8Imm:$S8), + "$Rd = mux($Pu, #$s8, #$S8)" , + [(set (i32 IntRegs:$Rd), + (i32 (select I1:$Pu, s8ExtPred:$s8, s8ImmPred:$S8)))] > { + bits<5> Rd; + bits<2> Pu; + bits<8> s8; + bits<8> S8; + + let IClass = 0b0111; + + let Inst{27-25} = 0b101; + let Inst{24-23} = Pu; + let Inst{22-16} = S8{7-1}; + let Inst{13} = S8{0}; + let Inst{12-5} = s8; + let Inst{4-0} = Rd; + } + let hasSideEffects = 0 in def COMBINE_ii : ALU32_ii<(outs DoubleRegs:$dst), (ins s8Imm:$src1, s8Imm:$src2), @@ -750,32 +808,6 @@ def VMUX_prr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1, "$dst = vmux($src1, $src2, $src3)", []>; -let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8, -CextOpcode = "MUX", InputType = "imm" in -def MUX_ir : ALU32_ir<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Ext:$src2, - IntRegs:$src3), - "$dst = mux($src1, #$src2, $src3)", - [(set (i32 IntRegs:$dst), - (i32 (select (i1 PredRegs:$src1), s8ExtPred:$src2, - (i32 IntRegs:$src3))))]>, ImmRegRel; - -let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 8, -CextOpcode = "MUX", InputType = "imm" in -def MUX_ri : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, - s8Ext:$src3), - "$dst = mux($src1, $src2, #$src3)", - [(set (i32 IntRegs:$dst), - (i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2), - s8ExtPred:$src3)))]>, ImmRegRel; - -let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8 in -def MUX_ii : ALU32_ii<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Ext:$src2, - s8Imm:$src3), - "$dst = mux($src1, #$src2, #$src3)", - [(set (i32 IntRegs:$dst), (i32 (select (i1 PredRegs:$src1), - s8ExtPred:$src2, - s8ImmPred:$src3)))]>; - def : Pat <(shl (i32 IntRegs:$src1), (i32 16)), (A2_aslh IntRegs:$src1)>; @@ -2659,7 +2691,7 @@ def : Pat<(store (i1 -1), ADDRriS11_2:$addr), // Map from memb(Rs) = Pd -> Rt = mux(Pd, #0, #1); store Rt. def : Pat<(store (i1 PredRegs:$src1), ADDRriS11_2:$addr), - (STrib ADDRriS11_2:$addr, (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0)) )>; + (STrib ADDRriS11_2:$addr, (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0)) )>; // Map Rdd = anyext(Rs) -> Rdd = sxtw(Rs). // Hexagon_TODO: We can probably use combine but that will cost 2 instructions. @@ -2779,11 +2811,11 @@ def : Pat <(i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))), // Sign extends. // i1 -> i32 def : Pat <(i32 (sext (i1 PredRegs:$src1))), - (i32 (MUX_ii (i1 PredRegs:$src1), -1, 0))>; + (i32 (C2_muxii (i1 PredRegs:$src1), -1, 0))>; // i1 -> i64 def : Pat <(i64 (sext (i1 PredRegs:$src1))), - (i64 (COMBINE_rr (TFRI -1), (MUX_ii (i1 PredRegs:$src1), -1, 0)))>; + (i64 (COMBINE_rr (TFRI -1), (C2_muxii (i1 PredRegs:$src1), -1, 0)))>; // Convert sign-extended load back to load and sign extend. // i8 -> i64 @@ -2809,11 +2841,11 @@ def: Pat <(i64 (sextloadi32 ADDRriS11_2:$src1)), // Zero extends. // i1 -> i32 def : Pat <(i32 (zext (i1 PredRegs:$src1))), - (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>; + (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0))>; // i1 -> i64 def : Pat <(i64 (zext (i1 PredRegs:$src1))), - (i64 (COMBINE_rr (TFRI 0), (MUX_ii (i1 PredRegs:$src1), 1, 0)))>, + (i64 (COMBINE_rr (TFRI 0), (C2_muxii (i1 PredRegs:$src1), 1, 0)))>, Requires<[NoV4T]>; // i32 -> i64 @@ -2874,15 +2906,15 @@ def: Pat <(i32 (zextloadi1 ADDRriS11_0:$src1)), // Map from Rs = Pd to Pd = mux(Pd, #1, #0) def : Pat <(i32 (zext (i1 PredRegs:$src1))), - (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>; + (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0))>; // Map from Rs = Pd to Pd = mux(Pd, #1, #0) def : Pat <(i32 (anyext (i1 PredRegs:$src1))), - (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>; + (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0))>; // Map from Rss = Pd to Rdd = sxtw (mux(Pd, #1, #0)) def : Pat <(i64 (anyext (i1 PredRegs:$src1))), - (i64 (SXTW (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))))>; + (i64 (SXTW (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0))))>; let AddedComplexity = 100 in diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td b/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td index 86acdec..6b8ce21 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td @@ -118,7 +118,7 @@ def V4_A4_rcmpeqi : ALU32_ri<(outs IntRegs:$Rd), // Preserve the TSTBIT generation def : Pat <(i32 (zext (i1 (setne (i32 (and (i32 (shl 1, (i32 IntRegs:$src2))), (i32 IntRegs:$src1))), 0)))), - (i32 (MUX_ii (i1 (TSTBIT_rr (i32 IntRegs:$src1), (i32 IntRegs:$src2))), + (i32 (C2_muxii (i1 (TSTBIT_rr (i32 IntRegs:$src1), (i32 IntRegs:$src2))), 1, 0))>; // Interfered with tstbit generation, above pattern preserves, see : tstbit.ll @@ -377,7 +377,7 @@ def : Pat <(i32 (load (add IntRegs:$src1, IntRegs:$src2))), // zext i1->i64 def : Pat <(i64 (zext (i1 PredRegs:$src1))), - (i64 (COMBINE_Ir_V4 0, (MUX_ii (i1 PredRegs:$src1), 1, 0)))>, + (i64 (COMBINE_Ir_V4 0, (C2_muxii (i1 PredRegs:$src1), 1, 0)))>, Requires<[HasV4T]>; // zext i32->i64 @@ -2449,7 +2449,7 @@ def : Pat <(i32 (zext (i1 (setle (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))), let AddedComplexity = 139 in def : Pat <(i32 (zext (i1 (setult (i32 (and (i32 IntRegs:$src1), 255)), u7StrictPosImmPred:$src2)))), - (i32 (MUX_ii (i1 (CMPbGTUri_V4 (i32 IntRegs:$src1), + (i32 (C2_muxii (i1 (CMPbGTUri_V4 (i32 IntRegs:$src1), (DEC_CONST_BYTE u7StrictPosImmPred:$src2))), 0, 1))>, Requires<[HasV4T]>; diff --git a/llvm/lib/Target/Hexagon/HexagonPeephole.cpp b/llvm/lib/Target/Hexagon/HexagonPeephole.cpp index a7a9675..cebb6c3 100644 --- a/llvm/lib/Target/Hexagon/HexagonPeephole.cpp +++ b/llvm/lib/Target/Hexagon/HexagonPeephole.cpp @@ -270,7 +270,7 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) { switch (Op) { case Hexagon::C2_mux: - case Hexagon::MUX_ii: + case Hexagon::C2_muxii: case Hexagon::TFR_condset_ii: NewOp = Op; break; @@ -280,11 +280,11 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) { case Hexagon::TFR_condset_ir: NewOp = Hexagon::TFR_condset_ri; break; - case Hexagon::MUX_ri: - NewOp = Hexagon::MUX_ir; + case Hexagon::C2_muxri: + NewOp = Hexagon::C2_muxir; break; - case Hexagon::MUX_ir: - NewOp = Hexagon::MUX_ri; + case Hexagon::C2_muxir: + NewOp = Hexagon::C2_muxri; break; } if (NewOp) { diff --git a/llvm/test/MC/Disassembler/Hexagon/alu32_perm.txt b/llvm/test/MC/Disassembler/Hexagon/alu32_perm.txt index b6009a4..fce6f8d 100644 --- a/llvm/test/MC/Disassembler/Hexagon/alu32_perm.txt +++ b/llvm/test/MC/Disassembler/Hexagon/alu32_perm.txt @@ -10,6 +10,14 @@ # CHECK: r17 = combine(r31.l, r21.l) 0xb0 0xe2 0x0f 0x7c # CHECK: r17:16 = combine(#21, #31) +0xf1 0xc3 0x75 0x73 +# CHECK: r17 = mux(p3, r21, #31) +0xb1 0xc2 0xff 0x73 +# CHECK: r17 = mux(p3, #21, r31) +0xb1 0xe2 0x8f 0x7b +# CHECK: r17 = mux(p3, #21, #31) +0x71 0xdf 0x15 0xf4 +# CHECK: r17 = mux(p3, r21, r31) 0x11 0xc0 0x15 0x70 # CHECK: r17 = aslh(r21) 0x11 0xc0 0x35 0x70 -- 2.7.4