From 965ba4291a6d978c7d4d98831d6ae62e9761f37d Mon Sep 17 00:00:00 2001 From: Sam Parker Date: Thu, 27 Feb 2020 15:36:53 +0000 Subject: [PATCH] Revert "[ARM] Add CPSR as an implicit use of t2IT" This reverts commit e58229fded0407f3e4f77cd87bedcd4d35bb7c89. Differential Revision: https://reviews.llvm.org/D75186 --- llvm/lib/Target/ARM/ARMInstrThumb2.td | 2 +- .../test/CodeGen/ARM/constant-islands-split-IT.mir | 6 +++--- llvm/test/CodeGen/ARM/tail-dup-bundle.mir | 2 +- llvm/test/CodeGen/MIR/ARM/bundled-instructions.mir | 9 ++++----- .../MIR/ARM/nested-instruction-bundle-error.mir | 2 +- .../CodeGen/Thumb2/LowOverheadLoops/cmplx_cong.mir | 6 +++--- .../Thumb2/LowOverheadLoops/dont-ignore-vctp.mir | 5 ++--- .../LowOverheadLoops/dont-remove-loop-update.mir | 4 ++-- .../LowOverheadLoops/dont-remove-loop-update2.mir | 22 ++++++++++------------ .../Thumb2/LowOverheadLoops/extract-element.mir | 4 ++-- .../Thumb2/LowOverheadLoops/incorrect-sub-16.mir | 4 ++-- .../Thumb2/LowOverheadLoops/incorrect-sub-32.mir | 4 ++-- .../Thumb2/LowOverheadLoops/incorrect-sub-8.mir | 4 ++-- .../Thumb2/LowOverheadLoops/it-block-chain.mir | 4 ++-- .../Thumb2/LowOverheadLoops/it-block-itercount.mir | 2 +- .../Thumb2/LowOverheadLoops/it-block-mov.mir | 8 ++++---- .../Thumb2/LowOverheadLoops/it-block-random.mir | 4 ++-- .../CodeGen/Thumb2/LowOverheadLoops/massive.mir | 2 +- .../CodeGen/Thumb2/LowOverheadLoops/matrix.mir | 8 ++++---- .../Thumb2/LowOverheadLoops/mov-lr-terminator.mir | 4 ++-- .../LowOverheadLoops/move-def-before-start.mir | 4 ++-- .../LowOverheadLoops/move-start-after-def.mir | 4 ++-- .../Thumb2/LowOverheadLoops/multiblock-massive.mir | 2 +- .../Thumb2/LowOverheadLoops/no-dec-cbnz.mir | 6 +++--- .../Thumb2/LowOverheadLoops/no-dec-reorder.mir | 10 +++++----- .../CodeGen/Thumb2/LowOverheadLoops/no-dec.mir | 2 +- .../Thumb2/LowOverheadLoops/no-vpsel-liveout.mir | 4 ++-- .../Thumb2/LowOverheadLoops/non-masked-load.mir | 4 ++-- .../Thumb2/LowOverheadLoops/non-masked-store.mir | 4 ++-- .../Thumb2/LowOverheadLoops/remove-elem-moves.mir | 8 ++++---- .../Thumb2/LowOverheadLoops/revert-non-header.mir | 4 ++-- .../CodeGen/Thumb2/LowOverheadLoops/size-limit.mir | 4 ++-- .../CodeGen/Thumb2/LowOverheadLoops/switch.mir | 2 +- .../LowOverheadLoops/unrolled-and-vector.mir | 4 ++-- .../LowOverheadLoops/unsafe-cpsr-loop-def.mir | 4 ++-- .../LowOverheadLoops/unsafe-cpsr-loop-use.mir | 4 ++-- .../LowOverheadLoops/vctp-add-operand-liveout.mir | 4 ++-- .../CodeGen/Thumb2/LowOverheadLoops/vctp-subi3.mir | 4 ++-- .../CodeGen/Thumb2/LowOverheadLoops/vctp-subri.mir | 4 ++-- .../Thumb2/LowOverheadLoops/vctp-subri12.mir | 4 ++-- .../Thumb2/LowOverheadLoops/vctp16-reduce.mir | 4 ++-- .../LowOverheadLoops/wrong-liveout-lsr-shift.mir | 4 ++-- .../LowOverheadLoops/wrong-vctp-opcode-liveout.mir | 4 ++-- .../wrong-vctp-operand-liveout.mir | 4 ++-- llvm/test/CodeGen/Thumb2/constant-islands-cbz.mir | 4 ++-- llvm/test/CodeGen/Thumb2/t2-teq-reduce.mir | 6 +++--- 46 files changed, 107 insertions(+), 111 deletions(-) diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td index 9c50988..1a9237b 100644 --- a/llvm/lib/Target/ARM/ARMInstrThumb2.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td @@ -3851,7 +3851,7 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { } // IT block -let Defs = [ITSTATE], Uses = [CPSR] in +let Defs = [ITSTATE] in def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask), AddrModeNone, 2, IIC_iALUx, "it$mask\t$cc", "", []>, diff --git a/llvm/test/CodeGen/ARM/constant-islands-split-IT.mir b/llvm/test/CodeGen/ARM/constant-islands-split-IT.mir index 6dd5805..82eee55 100644 --- a/llvm/test/CodeGen/ARM/constant-islands-split-IT.mir +++ b/llvm/test/CodeGen/ARM/constant-islands-split-IT.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -run-pass=arm-cp-islands %s -o - --verify-machineinstrs | FileCheck %s +# RUN: llc -run-pass=arm-cp-islands %s -o - | FileCheck %s # This test make sure that the constant pool does not keep in the middle of an IT block # when needs to split a block to place them. @@ -131,12 +131,12 @@ body: | renamable $r0 = t2MOVi 0, 14, _, _ t2CMPri $r0, 32, 14, $noreg, implicit-def $cpsr renamable $r0 = SPACE 200, undef renamable $r0 - t2IT 0, 1, implicit-def $itstate, implicit $cpsr + t2IT 0, 1, implicit-def $itstate renamable $d0 = VLDRD %const.1, 0, 0, $cpsr, implicit $itstate :: (load 8 from constant-pool) renamable $d1 = VLDRD %const.2, 0, 0, $cpsr, implicit $itstate :: (load 8 from constant-pool) renamable $d2 = VLDRD %const.0, 0, 0, $cpsr, implicit $itstate :: (load 8 from constant-pool) $r0 = t2SUBri $r0, 12, 0, $cpsr, $noreg, implicit killed $itstate - t2IT 0, 4, implicit-def $itstate, implicit $cpsr + t2IT 0, 4, implicit-def $itstate $sp = tMOVr $r0, 0, $cpsr, implicit $itstate $sp = t2LDMIA_RET $sp, 0, killed $cpsr, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc, implicit killed $d0, implicit killed $d1, implicit killed $d2, implicit $sp, implicit killed $itstate tBL 14, $noreg, &__stack_chk_fail, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp diff --git a/llvm/test/CodeGen/ARM/tail-dup-bundle.mir b/llvm/test/CodeGen/ARM/tail-dup-bundle.mir index 710d50a..9f539b6 100644 --- a/llvm/test/CodeGen/ARM/tail-dup-bundle.mir +++ b/llvm/test/CodeGen/ARM/tail-dup-bundle.mir @@ -42,7 +42,7 @@ body: | t2CMPri $r0, 32, 14, $noreg, implicit-def $cpsr BUNDLE implicit-def dead $itstate, implicit-def $cpsr, implicit killed $r0, implicit killed $cpsr { - t2IT 1, 24, implicit-def $itstate, implicit $cpsr + t2IT 1, 24, implicit-def $itstate t2CMPri killed $r0, 9, 1, killed $cpsr, implicit-def $cpsr, implicit internal killed $itstate } t2Bcc %bb.3, 1, killed $cpsr diff --git a/llvm/test/CodeGen/MIR/ARM/bundled-instructions.mir b/llvm/test/CodeGen/MIR/ARM/bundled-instructions.mir index 5948862..b7147d4 100644 --- a/llvm/test/CodeGen/MIR/ARM/bundled-instructions.mir +++ b/llvm/test/CodeGen/MIR/ARM/bundled-instructions.mir @@ -33,7 +33,7 @@ body: | ; CHECK: $r1 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg ; CHECK: t2CMNri killed $r0, 78, 14 /* CC::al */, $noreg, implicit-def $cpsr ; CHECK: BUNDLE implicit-def dead $itstate, implicit-def $r1, implicit killed $cpsr { - ; CHECK: t2IT 12, 8, implicit-def $itstate, implicit $cpsr + ; CHECK: t2IT 12, 8, implicit-def $itstate ; CHECK: $r1 = t2MOVi 1, 12 /* CC::gt */, killed $cpsr, $noreg, implicit internal killed $itstate ; CHECK: } ; CHECK: $r0 = tMOVr killed $r1, 14 /* CC::al */, $noreg @@ -41,7 +41,7 @@ body: | $r1 = t2MOVi 0, 14, _, _ t2CMNri killed $r0, 78, 14, _, implicit-def $cpsr BUNDLE implicit-def dead $itstate, implicit-def $r1, implicit killed $cpsr { - t2IT 12, 8, implicit-def $itstate, implicit $cpsr + t2IT 12, 8, implicit-def $itstate $r1 = t2MOVi 1, 12, killed $cpsr, _, implicit internal killed $itstate } $r0 = tMOVr killed $r1, 14, _ @@ -64,15 +64,14 @@ body: | ; CHECK: $r1 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg ; CHECK: t2CMNri killed $r0, 78, 14 /* CC::al */, $noreg, implicit-def $cpsr ; CHECK: BUNDLE implicit-def dead $itstate, implicit-def $r1, implicit killed $cpsr { - ; CHECK: t2IT 12, 8, implicit-def $itstate, implicit $cpsr + ; CHECK: t2IT 12, 8, implicit-def $itstate ; CHECK: $r1 = t2MOVi 1, 12 /* CC::gt */, killed $cpsr, $noreg, implicit internal killed $itstate ; CHECK: } ; CHECK: $r0 = tMOVr killed $r1, 14 /* CC::al */, $noreg ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0 $r1 = t2MOVi 0, 14, _, _ t2CMNri killed $r0, 78, 14, _, implicit-def $cpsr - BUNDLE implicit-def dead $itstate, implicit-def $r1, implicit killed $cpsr { - t2IT 12, 8, implicit-def $itstate, implicit $cpsr + BUNDLE implicit-def dead $itstate, implicit-def $r1, implicit killed $cpsr { t2IT 12, 8, implicit-def $itstate $r1 = t2MOVi 1, 12, killed $cpsr, _, internal implicit killed $itstate } $r0 = tMOVr killed $r1, 14, _ tBX_RET 14, _, implicit killed $r0 diff --git a/llvm/test/CodeGen/MIR/ARM/nested-instruction-bundle-error.mir b/llvm/test/CodeGen/MIR/ARM/nested-instruction-bundle-error.mir index b88adae..f05af43 100644 --- a/llvm/test/CodeGen/MIR/ARM/nested-instruction-bundle-error.mir +++ b/llvm/test/CodeGen/MIR/ARM/nested-instruction-bundle-error.mir @@ -19,7 +19,7 @@ body: | $r1 = t2MOVi 0, 14, _, _ t2CMNri killed $r0, 78, 14, _, implicit-def $cpsr BUNDLE implicit-def dead $itstate, implicit-def $r1, implicit killed $cpsr { - t2IT 12, 8, implicit-def $itstate, implicit $cpsr + t2IT 12, 8, implicit-def $itstate $r1 = t2MOVi 1, 12, killed $cpsr, _ ; CHECK: [[@LINE+1]]:14: nested instruction bundles are not allowed BUNDLE { diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/cmplx_cong.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/cmplx_cong.mir index 6e48c24..c27af57 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/cmplx_cong.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/cmplx_cong.mir @@ -38,13 +38,13 @@ body: | ; CHECK-LABEL: name: arm_cmplx_conj_f32_mve ; CHECK: bb.0: ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r4 + ; CHECK: liveins: $lr, $r0, $r1, $r3, $r4 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 - ; CHECK: renamable $r3, dead $cpsr = tLSLri killed renamable $r2, 1, 14 /* CC::al */, $noreg ; CHECK: tCMPi8 renamable $r3, 4, 14 /* CC::al */, $noreg, implicit-def dead $cpsr + ; FIXME: tLSRi needs to be producing the value in r3 ; CHECK: $r4 = t2MOVi16 target-flags(arm-lo16) @arm_cmplx_conj_f32_mve.cmplx_conj_sign, 14 /* CC::al */, $noreg ; CHECK: $r4 = t2MOVTi16 killed $r4, target-flags(arm-hi16) @arm_cmplx_conj_f32_mve.cmplx_conj_sign, 14 /* CC::al */, $noreg ; CHECK: renamable $q0 = nnan ninf nsz MVE_VLDRWU32 killed renamable $r4, 0, 0, $noreg @@ -71,7 +71,7 @@ body: | renamable $r12 = t2MOVi 4, 14 /* CC::al */, $noreg, $noreg renamable $r3, dead $cpsr = tLSLri renamable $r2, 1, 14 /* CC::al */, $noreg tCMPi8 renamable $r3, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr - t2IT 11, 8, implicit-def $itstate, implicit $cpsr + t2IT 11, 8, implicit-def $itstate $r12 = t2LSLri renamable $r2, 1, 11 /* CC::lt */, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14 /* CC::al */, $noreg, $noreg $r4 = t2MOVi16 target-flags(arm-lo16) @arm_cmplx_conj_f32_mve.cmplx_conj_sign, 14 /* CC::al */, $noreg diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-ignore-vctp.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-ignore-vctp.mir index 64234f5..09040ec 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-ignore-vctp.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-ignore-vctp.mir @@ -95,12 +95,11 @@ body: | ; CHECK-LABEL: name: dont_ignore_vctp ; CHECK: bb.0.entry: ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 + ; CHECK: liveins: $lr, $r0, $r1, $r3, $r7 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: renamable $r3, dead $cpsr = tLSLri killed renamable $r2, 1, 14 /* CC::al */, $noreg ; CHECK: tCMPi8 renamable $r3, 4, 14 /* CC::al */, $noreg, implicit-def dead $cpsr ; CHECK: renamable $r2 = tLEApcrel %const.0, 14 /* CC::al */, $noreg ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg :: (load 16 from constant-pool) @@ -129,7 +128,7 @@ body: | renamable $r3, dead $cpsr = tLSLri renamable $r2, 1, 14, $noreg renamable $r12 = t2MOVi 4, 14, $noreg, $noreg tCMPi8 renamable $r3, 4, 14, $noreg, implicit-def $cpsr - t2IT 11, 8, implicit-def $itstate, implicit $cpsr + t2IT 11, 8, implicit-def $itstate $r12 = t2LSLri renamable $r2, 1, 11, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14, $noreg, $noreg renamable $r12 = t2ADDri killed renamable $r2, 3, 14, $noreg, $noreg diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update.mir index 27b7094..5f007aa 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update.mir @@ -113,7 +113,7 @@ body: | ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 ; CHECK: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 11, 8, implicit-def $itstate, implicit $cpsr + ; CHECK: t2IT 11, 8, implicit-def $itstate ; CHECK: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate ; CHECK: renamable $r12 = t2ADDri renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg @@ -147,7 +147,7 @@ body: | $r7 = frame-setup tMOVr $sp, 14, $noreg frame-setup CFI_INSTRUCTION def_cfa_register $r7 tCMPi8 renamable $r3, 1, 14, $noreg, implicit-def $cpsr - t2IT 11, 8, implicit-def $itstate, implicit $cpsr + t2IT 11, 8, implicit-def $itstate tPOP_RET 11, killed $cpsr, def $r7, def $pc, implicit killed $itstate renamable $r12 = t2ADDri renamable $r3, 3, 14, $noreg, $noreg renamable $lr = t2MOVi 1, 14, $noreg, $noreg diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update2.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update2.mir index d66750a..f642c79 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update2.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update2.mir @@ -106,23 +106,22 @@ body: | ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 ; CHECK: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 11, 8, implicit-def $itstate, implicit $cpsr + ; CHECK: t2IT 11, 8, implicit-def $itstate ; CHECK: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r4, def $pc, implicit killed $itstate ; CHECK: $lr = MVE_DLSTP_32 renamable $r3 ; CHECK: bb.1.vector.body: ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 ; CHECK: renamable $r3, $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg - ; CHECK: t2IT 11, 8, implicit-def $itstate, implicit $cpsr - ; CHECK: tPOP_RET 11 /* CC::lt */, $cpsr, def $r4, def $pc, implicit killed $itstate + ; CHECK: t2IT 11, 8, implicit-def $itstate + ; CHECK: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r4, def $pc, implicit killed $itstate ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg :: (load 16 from %ir.lsr.iv13, align 4) ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg :: (load 16 from %ir.lsr.iv1416, align 4) ; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg :: (store 16 into %ir.lsr.iv1719, align 4) ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 ; CHECK: bb.2.for.cond.cleanup: - ; CHECK: liveins: $cpsr - ; CHECK: t2IT 11, 8, implicit-def dead $itstate, implicit killed $cpsr + ; CHECK: t2IT 11, 8, implicit-def dead $itstate ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc bb.0.entry: successors: %bb.1(0x80000000) @@ -133,8 +132,8 @@ body: | frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $r4, -8 tCMPi8 renamable $r3, 1, 14, $noreg, implicit-def $cpsr - t2IT 11, 8, implicit-def $itstate, implicit $cpsr - tPOP_RET 11, $cpsr, def $r4, def $pc, implicit killed $itstate + t2IT 11, 8, implicit-def $itstate + tPOP_RET 11, killed $cpsr, def $r4, def $pc, implicit killed $itstate renamable $r12 = t2ADDri renamable $r3, 3, 14, $noreg, $noreg renamable $lr = t2MOVi 1, 14, $noreg, $noreg renamable $r12 = t2BICri killed renamable $r12, 3, 14, $noreg, $noreg @@ -145,13 +144,13 @@ body: | bb.1.vector.body: successors: %bb.1(0x7c000000), %bb.2(0x04000000) - liveins: $r0, $r1, $r2, $r3, $r12, $cpsr + liveins: $r0, $r1, $r2, $r3, $r12 renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg $lr = tMOVr $r12, 14, $noreg renamable $r12 = nsw t2SUBri killed $r12, 1, 14, $noreg, $noreg renamable $r3, $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg - t2IT 11, 8, implicit-def $itstate, implicit $cpsr + t2IT 11, 8, implicit-def $itstate tPOP_RET 11, killed $cpsr, def $r4, def $pc, implicit killed $itstate MVE_VPST 4, implicit $vpr renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv13, align 4) @@ -160,12 +159,11 @@ body: | renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 MVE_VPST 8, implicit $vpr renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1719, align 4) - t2LoopEnd killed renamable $lr, %bb.1, implicit-def $cpsr + t2LoopEnd killed renamable $lr, %bb.1, implicit-def dead $cpsr tB %bb.2, 14, $noreg bb.2.for.cond.cleanup: - liveins: $cpsr - t2IT 11, 8, implicit-def $itstate, implicit $cpsr + t2IT 11, 8, implicit-def $itstate tPOP_RET 14, $noreg, def $r4, def $pc ... diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/extract-element.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/extract-element.mir index 4f91e6a..3a27e94 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/extract-element.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/extract-element.mir @@ -108,7 +108,7 @@ body: | ; CHECK: successors: %bb.1(0x80000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 0, 4, implicit-def $itstate, implicit $cpsr + ; CHECK: t2IT 0, 4, implicit-def $itstate ; CHECK: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate ; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp @@ -145,7 +145,7 @@ body: | liveins: $r0, $r1, $r2, $lr, $r7 tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr - t2IT 0, 4, implicit-def $itstate, implicit $cpsr + t2IT 0, 4, implicit-def $itstate renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-16.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-16.mir index 301b7f1..479d7f2 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-16.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-16.mir @@ -103,7 +103,7 @@ body: | ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 11, 8, implicit-def $itstate, implicit $cpsr + ; CHECK: t2IT 11, 8, implicit-def $itstate ; CHECK: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate ; CHECK: renamable $r12 = t2ADDri renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg @@ -134,7 +134,7 @@ body: | frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $r7, -8 tCMPi8 renamable $r3, 1, 14, $noreg, implicit-def $cpsr - t2IT 11, 8, implicit-def $itstate, implicit $cpsr + t2IT 11, 8, implicit-def $itstate tPOP_RET 11, killed $cpsr, def $r7, def $pc, implicit killed $itstate renamable $r12 = t2ADDri renamable $r3, 3, 14, $noreg, $noreg renamable $lr = t2MOVi 1, 14, $noreg, $noreg diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-32.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-32.mir index 70c869d..750397e 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-32.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-32.mir @@ -111,7 +111,7 @@ body: | ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 11, 8, implicit-def $itstate, implicit $cpsr + ; CHECK: t2IT 11, 8, implicit-def $itstate ; CHECK: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate ; CHECK: renamable $r12 = t2ADDri renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg @@ -142,7 +142,7 @@ body: | frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $r7, -8 tCMPi8 renamable $r3, 1, 14, $noreg, implicit-def $cpsr - t2IT 11, 8, implicit-def $itstate, implicit $cpsr + t2IT 11, 8, implicit-def $itstate tPOP_RET 11, killed $cpsr, def $r7, def $pc, implicit killed $itstate renamable $r12 = t2ADDri renamable $r3, 3, 14, $noreg, $noreg renamable $lr = t2MOVi 1, 14, $noreg, $noreg diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-8.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-8.mir index dc7319e..602c2c5 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-8.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-8.mir @@ -104,7 +104,7 @@ body: | ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 11, 8, implicit-def $itstate, implicit $cpsr + ; CHECK: t2IT 11, 8, implicit-def $itstate ; CHECK: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate ; CHECK: renamable $r12 = t2ADDri renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg @@ -135,7 +135,7 @@ body: | frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $r7, -8 tCMPi8 renamable $r3, 1, 14, $noreg, implicit-def $cpsr - t2IT 11, 8, implicit-def $itstate, implicit $cpsr + t2IT 11, 8, implicit-def $itstate tPOP_RET 11, killed $cpsr, def $r7, def $pc, implicit killed $itstate renamable $r12 = t2ADDri renamable $r3, 3, 14, $noreg, $noreg renamable $lr = t2MOVi 1, 14, $noreg, $noreg diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-chain.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-chain.mir index a1e470f..3e30204 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-chain.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-chain.mir @@ -105,7 +105,7 @@ body: | ; CHECK: renamable $r3, dead $cpsr = tLSLri renamable $r2, 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r12 = t2MOVi 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: tCMPi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 11, 8, implicit-def $itstate, implicit $cpsr + ; CHECK: t2IT 11, 8, implicit-def $itstate ; CHECK: $r1 = t2ADDri renamable $r0, 3, 11 /* CC::lt */, $noreg, $noreg, implicit $itstate ; CHECK: $r3 = t2LSLri renamable $r2, 1, 11 /* CC::lt */, $cpsr, $noreg, implicit renamable $r12, implicit $itstate ; CHECK: $r12 = t2LSLri renamable $r3, 1, 11 /* CC::lt */, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate @@ -139,7 +139,7 @@ body: | renamable $r3, dead $cpsr = tLSLri renamable $r2, 1, 14, $noreg renamable $r12 = t2MOVi 4, 14, $noreg, $noreg tCMPi8 renamable $r3, 4, 14, $noreg, implicit-def $cpsr - t2IT 11, 8, implicit-def $itstate, implicit $cpsr + t2IT 11, 8, implicit-def $itstate $r1 = t2ADDri killed renamable $r0, 3, 11, $noreg, $noreg, implicit $itstate $r3 = t2LSLri renamable $r2, 1, 11, $cpsr, $noreg, implicit renamable $r12, implicit $itstate $r12 = t2LSLri renamable $r3, 1, 11, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-itercount.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-itercount.mir index 4131129..456fe59 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-itercount.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-itercount.mir @@ -133,7 +133,7 @@ body: | renamable $r3, dead $cpsr = tLSLri renamable $r2, 1, 14, $noreg renamable $r12 = t2MOVi 4, 14, $noreg, $noreg tCMPi8 renamable $r3, 4, 14, $noreg, implicit-def $cpsr - t2IT 11, 8, implicit-def $itstate, implicit $cpsr + t2IT 11, 8, implicit-def $itstate $r12 = t2LSLri renamable $r2, 1, 11, $cpsr, $noreg, implicit renamable $r12, implicit $itstate $r12 = t2LSLri renamable $r2, 1, 11, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14, $noreg, $noreg diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-mov.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-mov.mir index cb5c9f7..bed94f9 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-mov.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-mov.mir @@ -47,7 +47,7 @@ body: | ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 ; CHECK: tCMPi8 renamable $r1, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr ; CHECK: renamable $r3 = t2MOVi 4, 14 /* CC::al */, $noreg, $noreg - ; CHECK: t2IT 11, 8, implicit-def $itstate, implicit $cpsr + ; CHECK: t2IT 11, 8, implicit-def $itstate ; CHECK: dead $r3 = tMOVr renamable $r1, 11 /* CC::lt */, killed $cpsr, implicit killed renamable $r3, implicit killed $itstate ; CHECK: tCMPi8 renamable $r1, 2, 14 /* CC::al */, $noreg, implicit-def $cpsr ; CHECK: renamable $r12 = t2MOVi 4, 14 /* CC::al */, $noreg, $noreg @@ -62,7 +62,7 @@ body: | ; CHECK: liveins: $r0, $r1, $r2, $r12 ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg ; CHECK: tCMPi8 renamable $r1, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 11, 8, implicit-def $itstate, implicit $cpsr + ; CHECK: t2IT 11, 8, implicit-def $itstate ; CHECK: $r12 = tMOVr renamable $r1, 11 /* CC::lt */, killed $cpsr, implicit killed renamable $r12, implicit killed $itstate ; CHECK: renamable $r3 = t2SUBrr renamable $r1, killed renamable $r12, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 3, 14 /* CC::al */, $noreg @@ -122,7 +122,7 @@ body: | frame-setup CFI_INSTRUCTION offset $r4, -8 tCMPi8 renamable $r1, 4, 14, $noreg, implicit-def $cpsr renamable $r3 = t2MOVi 4, 14, $noreg, $noreg - t2IT 11, 8, implicit-def $itstate, implicit $cpsr + t2IT 11, 8, implicit-def $itstate $r3 = tMOVr renamable $r1, 11, killed $cpsr, implicit killed renamable $r3, implicit killed $itstate tCMPi8 renamable $r1, 2, 14, $noreg, implicit-def $cpsr renamable $r12 = t2MOVi 4, 14, $noreg, $noreg @@ -144,7 +144,7 @@ body: | renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 3, 14, $noreg tCMPi8 renamable $r1, 4, 14, $noreg, implicit-def $cpsr renamable $lr = nuw nsw t2ADDrs renamable $r4, killed renamable $r3, 19, 14, $noreg, $noreg - t2IT 11, 8, implicit-def $itstate, implicit $cpsr + t2IT 11, 8, implicit-def $itstate $r12 = tMOVr renamable $r1, 11, killed $cpsr, implicit killed renamable $r12, implicit killed $itstate renamable $r3 = t2SUBrr renamable $r1, killed renamable $r12, 14, $noreg, $noreg renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 3, 14, $noreg diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-random.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-random.mir index 4cb0309..d8f4030 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-random.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-random.mir @@ -107,7 +107,7 @@ body: | ; CHECK: renamable $r3, dead $cpsr = tLSLri renamable $r2, 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r12 = t2MOVi 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: tCMPi8 renamable $r3, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 11, 8, implicit-def $itstate, implicit $cpsr + ; CHECK: t2IT 11, 8, implicit-def $itstate ; CHECK: $r12 = t2LSLri renamable $r2, 1, 11 /* CC::lt */, $cpsr, $noreg, implicit killed renamable $r12, implicit $itstate ; CHECK: $r0 = t2ADDri killed renamable $r0, 42, 11 /* CC::lt */, killed $cpsr, $noreg, implicit killed renamable $r0, implicit killed $itstate ; CHECK: renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14 /* CC::al */, $noreg, $noreg @@ -140,7 +140,7 @@ body: | renamable $r3, dead $cpsr = tLSLri renamable $r2, 1, 14, $noreg renamable $r12 = t2MOVi 4, 14, $noreg, $noreg tCMPi8 renamable $r3, 4, 14, $noreg, implicit-def $cpsr - t2IT 11, 8, implicit-def $itstate, implicit $cpsr + t2IT 11, 8, implicit-def $itstate $r12 = t2LSLri renamable $r2, 1, 11, $cpsr, $noreg, implicit renamable $r12, implicit $itstate $r0 = t2ADDri renamable $r0, 42, 11, killed $cpsr, $noreg, implicit killed renamable $r0, implicit killed $itstate renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14, $noreg, $noreg diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/massive.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/massive.mir index 4a10fa0..74fb334 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/massive.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/massive.mir @@ -117,7 +117,7 @@ body: | frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $r7, -8 tCMPi8 $r3, 0, 14, $noreg, implicit-def $cpsr - t2IT 0, 8, implicit-def $itstate, implicit $cpsr + t2IT 0, 8, implicit-def $itstate tPOP_RET 0, killed $cpsr, def $r7, def $pc, implicit killed $itstate renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14, $noreg renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix.mir index 38b4d90..886fbe7 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix.mir @@ -249,7 +249,7 @@ body: | ; CHECK: renamable $r3 = t2CSINC $zr, $zr, 13, implicit killed $cpsr ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr ; CHECK: renamable $r3 = t2ANDrr killed renamable $r3, killed renamable $r7, 14 /* CC::al */, $noreg, $noreg - ; CHECK: t2IT 12, 8, implicit-def $itstate, implicit $cpsr + ; CHECK: t2IT 12, 8, implicit-def $itstate ; CHECK: $r2 = tMOVi8 $noreg, 0, 12 /* CC::gt */, killed $cpsr, implicit killed renamable $r2, implicit killed $itstate ; CHECK: renamable $r6 = tADDhirr killed renamable $r6, killed renamable $r3, 14 /* CC::al */, $noreg ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 @@ -331,7 +331,7 @@ body: | ; CHECK: renamable $r2 = t2CSINC $zr, $zr, 13, implicit killed $cpsr ; CHECK: tCMPi8 renamable $r1, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr ; CHECK: renamable $r2 = t2ANDrr killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: t2IT 12, 8, implicit-def $itstate, implicit $cpsr + ; CHECK: t2IT 12, 8, implicit-def $itstate ; CHECK: $r1 = tMOVi8 $noreg, 0, 12 /* CC::gt */, killed $cpsr, implicit killed renamable $r1, implicit killed $itstate ; CHECK: renamable $r0 = tADDhirr killed renamable $r0, killed renamable $r2, 14 /* CC::al */, $noreg ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.10 @@ -400,7 +400,7 @@ body: | renamable $r3 = t2CSINC $zr, $zr, 13, implicit killed $cpsr tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr renamable $r3 = t2ANDrr killed renamable $r3, killed renamable $r7, 14, $noreg, $noreg - t2IT 12, 8, implicit-def $itstate, implicit $cpsr + t2IT 12, 8, implicit-def $itstate $r2 = tMOVi8 $noreg, 0, 12, killed $cpsr, implicit killed renamable $r2, implicit killed $itstate renamable $r6 = tADDhirr killed renamable $r6, killed renamable $r3, 14, $noreg t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr @@ -503,7 +503,7 @@ body: | renamable $r2 = t2CSINC $zr, $zr, 13, implicit killed $cpsr tCMPi8 renamable $r1, 0, 14, $noreg, implicit-def $cpsr renamable $r2 = t2ANDrr killed renamable $r2, killed renamable $r3, 14, $noreg, $noreg - t2IT 12, 8, implicit-def $itstate, implicit $cpsr + t2IT 12, 8, implicit-def $itstate $r1 = tMOVi8 $noreg, 0, 12, killed $cpsr, implicit killed renamable $r1, implicit killed $itstate renamable $r0 = tADDhirr killed renamable $r0, killed renamable $r2, 14, $noreg t2LoopEnd renamable $lr, %bb.10, implicit-def dead $cpsr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-lr-terminator.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-lr-terminator.mir index 6a29e34..d53caa2 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-lr-terminator.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-lr-terminator.mir @@ -107,7 +107,7 @@ body: | ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 ; CHECK: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg ; CHECK: t2CMPrs killed renamable $r12, renamable $r3, 11, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 0, 8, implicit-def $itstate, implicit $cpsr + ; CHECK: t2IT 0, 8, implicit-def $itstate ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate ; CHECK: renamable $r12 = t2LSRri killed renamable $r3, 1, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg @@ -135,7 +135,7 @@ body: | frame-setup CFI_INSTRUCTION offset $r4, -8 renamable $r12 = t2MOVi 0, 14, $noreg, $noreg t2CMPrs killed renamable $r12, renamable $r3, 11, 14, $noreg, implicit-def $cpsr - t2IT 0, 8, implicit-def $itstate, implicit $cpsr + t2IT 0, 8, implicit-def $itstate tPOP_RET 0, killed $cpsr, def $r4, def $pc, implicit killed $itstate renamable $r12 = t2MOVi 3, 14, $noreg, $noreg renamable $lr = t2MOVi 1, 14, $noreg, $noreg diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-def-before-start.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-def-before-start.mir index ee5f902..f546226 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-def-before-start.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-def-before-start.mir @@ -112,7 +112,7 @@ body: | ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 ; CHECK: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg ; CHECK: t2CMPrs killed renamable $r12, renamable $r3, 11, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 0, 8, implicit-def $itstate, implicit $cpsr + ; CHECK: t2IT 0, 8, implicit-def $itstate ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate ; CHECK: $r12 = t2MOVr killed $r3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2LSRri killed renamable $r12, 1, 14 /* CC::al */, $noreg, $noreg @@ -141,7 +141,7 @@ body: | frame-setup CFI_INSTRUCTION offset $r4, -8 renamable $r12 = t2MOVi 0, 14, $noreg, $noreg t2CMPrs killed renamable $r12, renamable $r3, 11, 14, $noreg, implicit-def $cpsr - t2IT 0, 8, implicit-def $itstate, implicit $cpsr + t2IT 0, 8, implicit-def $itstate tPOP_RET 0, killed $cpsr, def $r4, def $pc, implicit killed $itstate renamable $r12 = t2MOVi 3, 14, $noreg, $noreg renamable $lr = t2MOVi 1, 14, $noreg, $noreg diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-start-after-def.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-start-after-def.mir index b6d783f..80def3f 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-start-after-def.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-start-after-def.mir @@ -112,7 +112,7 @@ body: | ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 ; CHECK: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg ; CHECK: t2CMPrs killed renamable $r12, renamable $r3, 11, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 0, 8, implicit-def $itstate, implicit $cpsr + ; CHECK: t2IT 0, 8, implicit-def $itstate ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate ; CHECK: renamable $r12 = t2MOVi 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = nuw t2ADDrs killed renamable $r12, renamable $r3, 11, 14 /* CC::al */, $noreg, $noreg @@ -145,7 +145,7 @@ body: | frame-setup CFI_INSTRUCTION offset $r4, -8 renamable $r12 = t2MOVi 0, 14, $noreg, $noreg t2CMPrs killed renamable $r12, renamable $r3, 11, 14, $noreg, implicit-def $cpsr - t2IT 0, 8, implicit-def $itstate, implicit $cpsr + t2IT 0, 8, implicit-def $itstate tPOP_RET 0, killed $cpsr, def $r4, def $pc, implicit killed $itstate renamable $r12 = t2MOVi 3, 14, $noreg, $noreg renamable $lr = t2MOVi 1, 14, $noreg, $noreg diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiblock-massive.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiblock-massive.mir index 4f4acde..2e3aa0d 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiblock-massive.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiblock-massive.mir @@ -121,7 +121,7 @@ body: | frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $r4, -8 tCMPi8 $r3, 0, 14, $noreg, implicit-def $cpsr - t2IT 0, 8, implicit-def $itstate, implicit $cpsr + t2IT 0, 8, implicit-def $itstate tPOP_RET 0, killed $cpsr, def $r4, def $pc, implicit killed $itstate $lr = tMOVr $r3, 14, $noreg t2DoLoopStart killed $r3 diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec-cbnz.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec-cbnz.mir index 63522ab..f8507e1 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec-cbnz.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec-cbnz.mir @@ -134,7 +134,7 @@ body: | ; CHECK-LOB: renamable $r2 = tLDRi renamable $r0, 1, 14 /* CC::al */, $noreg :: (load 4 from %ir.info2) ; CHECK-LOB: renamable $r2 = tLDRHi killed renamable $r2, 1, 14 /* CC::al */, $noreg :: (load 2 from %ir.idx3) ; CHECK-LOB: tCMPr killed renamable $r2, renamable $r1, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK-LOB: t2IT 0, 8, implicit-def $itstate, implicit $cpsr + ; CHECK-LOB: t2IT 0, 8, implicit-def $itstate ; CHECK-LOB: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate ; CHECK-LOB: renamable $r0 = tLDRi killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.next4) ; CHECK-LOB: tCBNZ $r0, %bb.8 @@ -187,7 +187,7 @@ body: | ; CHECK-NOLOB: renamable $r2 = tLDRi renamable $r0, 1, 14 /* CC::al */, $noreg :: (load 4 from %ir.info2) ; CHECK-NOLOB: renamable $r2 = tLDRHi killed renamable $r2, 1, 14 /* CC::al */, $noreg :: (load 2 from %ir.idx3) ; CHECK-NOLOB: tCMPr killed renamable $r2, renamable $r1, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK-NOLOB: t2IT 0, 8, implicit-def $itstate, implicit $cpsr + ; CHECK-NOLOB: t2IT 0, 8, implicit-def $itstate ; CHECK-NOLOB: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate ; CHECK-NOLOB: renamable $r0 = tLDRi killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.next4) ; CHECK-NOLOB: tCMPi8 renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr @@ -248,7 +248,7 @@ body: | renamable $r2 = tLDRi renamable $r0, 1, 14, $noreg :: (load 4 from %ir.info2) renamable $r2 = tLDRHi killed renamable $r2, 1, 14, $noreg :: (load 2 from %ir.idx3) tCMPr killed renamable $r2, renamable $r1, 14, $noreg, implicit-def $cpsr - t2IT 0, 8, implicit-def $itstate, implicit $cpsr + t2IT 0, 8, implicit-def $itstate tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.next4) tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec-reorder.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec-reorder.mir index 377cbca..ffabd94 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec-reorder.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec-reorder.mir @@ -125,7 +125,7 @@ body: | liveins: $r0, $r2 tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr - t2IT 0, 4, implicit-def $itstate, implicit $cpsr + t2IT 0, 4, implicit-def $itstate renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate renamable $r1 = tUXTH killed renamable $r2, 14, $noreg @@ -145,7 +145,7 @@ body: | renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.next4) tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr - t2IT 0, 4, implicit-def $itstate, implicit $cpsr + t2IT 0, 4, implicit-def $itstate renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate t2B %bb.4, 14, $noreg @@ -160,7 +160,7 @@ body: | liveins: $r0, $r1 tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr - t2IT 0, 4, implicit-def $itstate, implicit $cpsr + t2IT 0, 4, implicit-def $itstate renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate renamable $r1 = t2LDRSHi12 killed renamable $r1, 0, 14, $noreg :: (load 2 from %ir.data16143) @@ -172,11 +172,11 @@ body: | renamable $r2 = tLDRi renamable $r0, 1, 14, $noreg :: (load 4 from %ir.info12) renamable $r2 = tLDRBi killed renamable $r2, 0, 14, $noreg :: (load 1 from %ir.data166, align 2) tCMPr killed renamable $r2, renamable $r1, 14, $noreg, implicit-def $cpsr - t2IT 0, 8, implicit-def $itstate, implicit $cpsr + t2IT 0, 8, implicit-def $itstate tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.next205) tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr - t2IT 0, 4, implicit-def $itstate, implicit $cpsr + t2IT 0, 4, implicit-def $itstate renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate t2B %bb.2, 14, $noreg diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec.mir index 1db66f9..6d27494 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec.mir @@ -151,7 +151,7 @@ body: | renamable $r2 = tLDRi renamable $r0, 1, 14, $noreg :: (load 4 from %ir.info2) renamable $r2 = tLDRHi killed renamable $r2, 1, 14, $noreg :: (load 2 from %ir.idx3) tCMPr killed renamable $r2, renamable $r1, 14, $noreg, implicit-def $cpsr - t2IT 0, 8, implicit-def $itstate, implicit $cpsr + t2IT 0, 8, implicit-def $itstate tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.next4) tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-vpsel-liveout.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-vpsel-liveout.mir index 3528d83..d0bb6e4 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-vpsel-liveout.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-vpsel-liveout.mir @@ -105,7 +105,7 @@ body: | ; CHECK: successors: %bb.1(0x80000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 0, 4, implicit-def $itstate, implicit $cpsr + ; CHECK: t2IT 0, 4, implicit-def $itstate ; CHECK: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate ; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp @@ -142,7 +142,7 @@ body: | liveins: $r0, $r1, $r2, $lr, $r7 tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr - t2IT 0, 4, implicit-def $itstate, implicit $cpsr + t2IT 0, 4, implicit-def $itstate renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-load.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-load.mir index ac94ca6..c006add 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-load.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-load.mir @@ -110,7 +110,7 @@ body: | ; CHECK: successors: %bb.1(0x80000000) ; CHECK: liveins: $lr, $r0, $r1, $r2 ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 0, 2, implicit-def $itstate, implicit $cpsr + ; CHECK: t2IT 0, 2, implicit-def $itstate ; CHECK: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate ; CHECK: renamable $r0 = tUXTB killed renamable $r0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate ; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate @@ -154,7 +154,7 @@ body: | liveins: $r0, $r1, $r2, $lr tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr - t2IT 0, 2, implicit-def $itstate, implicit $cpsr + t2IT 0, 2, implicit-def $itstate renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate renamable $r0 = tUXTB killed renamable $r0, 0, $cpsr, implicit killed $r0, implicit $itstate tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-store.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-store.mir index 5f1f64a..45a0b2e 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-store.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-store.mir @@ -108,7 +108,7 @@ body: | ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 ; CHECK: tCMPi8 renamable $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 0, 8, implicit-def $itstate, implicit $cpsr + ; CHECK: t2IT 0, 8, implicit-def $itstate ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate ; CHECK: renamable $r12 = t2ADDri renamable $r3, 15, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg @@ -140,7 +140,7 @@ body: | $r7 = frame-setup tMOVr $sp, 14, $noreg frame-setup CFI_INSTRUCTION def_cfa_register $r7 tCMPi8 renamable $r3, 0, 14, $noreg, implicit-def $cpsr - t2IT 0, 8, implicit-def $itstate, implicit $cpsr + t2IT 0, 8, implicit-def $itstate tPOP_RET 0, killed $cpsr, def $r7, def $pc, implicit killed $itstate renamable $r12 = t2ADDri renamable $r3, 15, 14, $noreg, $noreg renamable $lr = t2MOVi 1, 14, $noreg, $noreg diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/remove-elem-moves.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/remove-elem-moves.mir index 2c705c7..fa799111 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/remove-elem-moves.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/remove-elem-moves.mir @@ -162,7 +162,7 @@ body: | ; CHECK: liveins: $r0, $r1, $r2 ; CHECK: renamable $r3 = t2ADDrs renamable $r0, renamable $r2, 18, 14 /* CC::al */, $noreg, $noreg ; CHECK: tCMPr killed renamable $r3, renamable $r1, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 8, 4, implicit-def $itstate, implicit $cpsr + ; CHECK: t2IT 8, 4, implicit-def $itstate ; CHECK: renamable $r3 = t2ADDrs renamable $r1, renamable $r2, 18, 8 /* CC::hi */, $cpsr, $noreg, implicit $itstate ; CHECK: tCMPr killed renamable $r3, renamable $r0, 8 /* CC::hi */, killed $cpsr, implicit-def $cpsr, implicit killed $itstate ; CHECK: tBcc %bb.6, 8 /* CC::hi */, killed $cpsr @@ -195,7 +195,7 @@ body: | ; CHECK: liveins: $r2, $r3, $r4, $r7, $r12 ; CHECK: tCMPr killed renamable $r4, killed renamable $r2, 14 /* CC::al */, $noreg, implicit-def $cpsr ; CHECK: $lr = tMOVr killed $r7, 14 /* CC::al */, $noreg - ; CHECK: t2IT 0, 8, implicit-def $itstate, implicit $cpsr + ; CHECK: t2IT 0, 8, implicit-def $itstate ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $r5, def $r7, def $pc, implicit killed $itstate ; CHECK: tB %bb.7, 14 /* CC::al */, $noreg ; CHECK: bb.6: @@ -247,7 +247,7 @@ body: | renamable $r3 = t2ADDrs renamable $r0, renamable $r2, 18, 14, $noreg, $noreg tCMPr killed renamable $r3, renamable $r1, 14, $noreg, implicit-def $cpsr - t2IT 8, 4, implicit-def $itstate, implicit $cpsr + t2IT 8, 4, implicit-def $itstate renamable $r3 = t2ADDrs renamable $r1, renamable $r2, 18, 8, $cpsr, $noreg, implicit $itstate tCMPr killed renamable $r3, renamable $r0, 8, killed $cpsr, implicit-def $cpsr, implicit killed $itstate tBcc %bb.6, 8, killed $cpsr @@ -287,7 +287,7 @@ body: | tCMPr killed renamable $r4, killed renamable $r2, 14, $noreg, implicit-def $cpsr $lr = tMOVr killed $r7, 14, $noreg - t2IT 0, 8, implicit-def $itstate, implicit $cpsr + t2IT 0, 8, implicit-def $itstate tPOP_RET 0, killed $cpsr, def $r4, def $r5, def $r7, def $pc, implicit killed $itstate tB %bb.7, 14, $noreg diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir index 9912cd3..c68e547 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir @@ -253,12 +253,12 @@ body: | renamable $r4 = tLDRr renamable $r3, $r6, 14, $noreg :: (load 4 from %ir.uglygep12) renamable $r2 = tLDRr renamable $r5, $r6, 14, $noreg :: (load 4 from %ir.uglygep34) tCMPr renamable $r2, renamable $r4, 14, $noreg, implicit-def $cpsr - t2IT 12, 1, implicit-def $itstate, implicit $cpsr + t2IT 12, 1, implicit-def $itstate tSTRr killed renamable $r4, renamable $r5, $r6, 12, $cpsr, implicit $itstate :: (store 4 into %ir.5) tSTRr killed renamable $r2, renamable $r3, $r6, 12, $cpsr, implicit $itstate :: (store 4 into %ir.uglygep6) renamable $r6 = tADDhirr killed renamable $r6, renamable $r10, 12, $cpsr, implicit $r6, implicit $itstate renamable $r7 = nsw t2SUBrr killed renamable $r7, renamable $r9, 12, $cpsr, $noreg, implicit $r7, implicit killed $itstate - t2IT 12, 8, implicit-def $itstate, implicit $cpsr + t2IT 12, 8, implicit-def $itstate t2CMPri renamable $r7, -1, 12, killed $cpsr, implicit-def $cpsr, implicit killed $itstate tBcc %bb.8, 12, killed $cpsr tB %bb.5, 14, $noreg diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir index 81f7b76..e6460ef 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir @@ -115,7 +115,7 @@ body: | ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: tCMPi8 $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 0, 8, implicit-def $itstate, implicit $cpsr + ; CHECK: t2IT 0, 8, implicit-def $itstate ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg @@ -141,7 +141,7 @@ body: | frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $r7, -8 tCMPi8 $r3, 0, 14, $noreg, implicit-def $cpsr - t2IT 0, 8, implicit-def $itstate, implicit $cpsr + t2IT 0, 8, implicit-def $itstate tPOP_RET 0, killed $cpsr, def $r7, def $pc, implicit killed $itstate renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14, $noreg renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/switch.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/switch.mir index 8e8092a..a97da0c 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/switch.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/switch.mir @@ -141,7 +141,7 @@ body: | liveins: $lr, $r0, $r1, $r2, $r3, $r12 tCMPi8 killed renamable $r3, 32, 14, $noreg, implicit-def $cpsr - t2IT 0, 8, implicit-def $itstate, implicit $cpsr + t2IT 0, 8, implicit-def $itstate renamable $r1 = nsw tADDi8 $noreg, killed renamable $r1, 1, 0, killed $cpsr, implicit $r1, implicit killed $itstate bb.3.for.inc: diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unrolled-and-vector.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unrolled-and-vector.mir index d0d0586..3a9aa03 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unrolled-and-vector.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unrolled-and-vector.mir @@ -265,7 +265,7 @@ body: | ; CHECK: renamable $r5 = t2CSINC $zr, $zr, 9, implicit killed $cpsr ; CHECK: renamable $r5, dead $cpsr = tAND killed renamable $r5, killed renamable $r4, 14 /* CC::al */, $noreg ; CHECK: dead renamable $r5, $cpsr = tLSLri killed renamable $r5, 31, 14 /* CC::al */, $noreg - ; CHECK: t2IT 0, 4, implicit-def $itstate, implicit $cpsr + ; CHECK: t2IT 0, 4, implicit-def $itstate ; CHECK: renamable $r6 = t2ANDrr killed renamable $r6, killed renamable $r12, 0 /* CC::eq */, $cpsr, $noreg, implicit killed $r6, implicit $itstate ; CHECK: dead renamable $r6 = t2LSLri killed renamable $r6, 31, 0 /* CC::eq */, killed $cpsr, def $cpsr, implicit killed $r6, implicit killed $itstate ; CHECK: tBcc %bb.4, 0 /* CC::eq */, killed $cpsr @@ -400,7 +400,7 @@ body: | renamable $r5 = t2CSINC $zr, $zr, 9, implicit killed $cpsr renamable $r5, dead $cpsr = tAND killed renamable $r5, killed renamable $r4, 14, $noreg dead renamable $r5, $cpsr = tLSLri killed renamable $r5, 31, 14, $noreg - t2IT 0, 4, implicit-def $itstate, implicit $cpsr + t2IT 0, 4, implicit-def $itstate renamable $r6 = t2ANDrr killed renamable $r6, killed renamable $r12, 0, $cpsr, $noreg, implicit $r6, implicit $itstate dead renamable $r6 = t2LSLri killed renamable $r6, 31, 0, killed $cpsr, def $cpsr, implicit killed $r6, implicit killed $itstate tBcc %bb.4, 0, killed $cpsr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-def.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-def.mir index 009ee30..db8f969 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-def.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-def.mir @@ -109,7 +109,7 @@ body: | ; CHECK: renamable $r3, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep7) ; CHECK: tCMPhir renamable $lr, renamable $r2, 14 /* CC::al */, $noreg, implicit-def $cpsr ; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg - ; CHECK: t2IT 2, 8, implicit-def $itstate, implicit $cpsr + ; CHECK: t2IT 2, 8, implicit-def $itstate ; CHECK: renamable $r3 = tLSRri $noreg, killed renamable $r3, 1, 2 /* CC::hs */, killed $cpsr, implicit renamable $r3, implicit killed $itstate ; CHECK: early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep4) ; CHECK: t2CMPri renamable $lr, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr @@ -139,7 +139,7 @@ body: | renamable $r3, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep7) tCMPhir renamable $lr, renamable $r2, 14, $noreg, implicit-def $cpsr renamable $lr = t2LoopDec killed renamable $lr, 1 - t2IT 2, 8, implicit-def $itstate, implicit $cpsr + t2IT 2, 8, implicit-def $itstate renamable $r3 = tLSRri $noreg, killed renamable $r3, 1, 2, killed $cpsr, implicit renamable $r3, implicit killed $itstate early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep4) t2CMPri renamable $lr, 0, 14, $noreg, implicit-def $cpsr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-use.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-use.mir index 53f8782..53e31be 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-use.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-use.mir @@ -109,7 +109,7 @@ body: | ; CHECK: renamable $r3, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep7) ; CHECK: tCMPhir renamable $lr, renamable $r2, 14 /* CC::al */, $noreg, implicit-def $cpsr ; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg - ; CHECK: t2IT 2, 8, implicit-def $itstate, implicit $cpsr + ; CHECK: t2IT 2, 8, implicit-def $itstate ; CHECK: renamable $r3 = tLSRri $noreg, killed renamable $r3, 1, 2 /* CC::hs */, killed $cpsr, implicit killed renamable $r3, implicit killed $itstate ; CHECK: early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep4) ; CHECK: renamable $lr = tMOVr killed $lr, 14 /* CC::al */, $noreg @@ -140,7 +140,7 @@ body: | renamable $r3, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep7) tCMPhir renamable $lr, renamable $r2, 14, $noreg, implicit-def $cpsr renamable $lr = t2LoopDec killed renamable $lr, 1 - t2IT 2, 8, implicit-def $itstate, implicit $cpsr + t2IT 2, 8, implicit-def $itstate renamable $r3 = tLSRri $noreg, killed renamable $r3, 1, 2, killed $cpsr, implicit renamable $r3, implicit killed $itstate early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep4) renamable $lr = tMOVr $lr, 14, $noreg diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-add-operand-liveout.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-add-operand-liveout.mir index 371e8cb..87cb8ea 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-add-operand-liveout.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-add-operand-liveout.mir @@ -112,7 +112,7 @@ body: | ; CHECK: successors: %bb.1(0x80000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 0, 4, implicit-def $itstate, implicit $cpsr + ; CHECK: t2IT 0, 4, implicit-def $itstate ; CHECK: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate ; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp @@ -153,7 +153,7 @@ body: | liveins: $r0, $r1, $r2, $lr, $r7 tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr - t2IT 0, 4, implicit-def $itstate, implicit $cpsr + t2IT 0, 4, implicit-def $itstate renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subi3.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subi3.mir index 927ec57..b339d54 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subi3.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subi3.mir @@ -106,7 +106,7 @@ body: | ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 11, 8, implicit-def $itstate, implicit $cpsr + ; CHECK: t2IT 11, 8, implicit-def $itstate ; CHECK: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 ; CHECK: bb.1.vector.body: @@ -128,7 +128,7 @@ body: | frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $r7, -8 tCMPi8 renamable $r3, 1, 14, $noreg, implicit-def $cpsr - t2IT 11, 8, implicit-def $itstate, implicit $cpsr + t2IT 11, 8, implicit-def $itstate tPOP_RET 11, killed $cpsr, def $r7, def $pc, implicit killed $itstate renamable $r12 = t2ADDri renamable $r3, 3, 14, $noreg, $noreg renamable $lr = t2MOVi 1, 14, $noreg, $noreg diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri.mir index b17468b..027bbb4 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri.mir @@ -105,7 +105,7 @@ body: | ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 11, 8, implicit-def $itstate, implicit $cpsr + ; CHECK: t2IT 11, 8, implicit-def $itstate ; CHECK: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 ; CHECK: bb.1.vector.body: @@ -127,7 +127,7 @@ body: | frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $r7, -8 tCMPi8 renamable $r3, 1, 14, $noreg, implicit-def $cpsr - t2IT 11, 8, implicit-def $itstate, implicit $cpsr + t2IT 11, 8, implicit-def $itstate tPOP_RET 11, killed $cpsr, def $r7, def $pc, implicit killed $itstate renamable $r12 = t2ADDri renamable $r3, 3, 14, $noreg, $noreg renamable $lr = t2MOVi 1, 14, $noreg, $noreg diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri12.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri12.mir index fc81c93..edb1bd3 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri12.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri12.mir @@ -105,7 +105,7 @@ body: | ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 11, 8, implicit-def $itstate, implicit $cpsr + ; CHECK: t2IT 11, 8, implicit-def $itstate ; CHECK: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 ; CHECK: bb.1.vector.body: @@ -127,7 +127,7 @@ body: | frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $r7, -8 tCMPi8 renamable $r3, 1, 14, $noreg, implicit-def $cpsr - t2IT 11, 8, implicit-def $itstate, implicit $cpsr + t2IT 11, 8, implicit-def $itstate tPOP_RET 11, killed $cpsr, def $r7, def $pc, implicit killed $itstate renamable $r12 = t2ADDri renamable $r3, 3, 14, $noreg, $noreg renamable $lr = t2MOVi 1, 14, $noreg, $noreg diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp16-reduce.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp16-reduce.mir index e40f35a..3de9bcc 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp16-reduce.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp16-reduce.mir @@ -115,7 +115,7 @@ body: | ; CHECK: successors: %bb.1(0x80000000) ; CHECK: liveins: $lr, $r0, $r1, $r2 ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 0, 2, implicit-def $itstate, implicit $cpsr + ; CHECK: t2IT 0, 2, implicit-def $itstate ; CHECK: renamable $r0 = t2MOVi16 32767, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate ; CHECK: renamable $r0 = tSXTH killed renamable $r0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate ; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate @@ -162,7 +162,7 @@ body: | liveins: $r0, $r1, $r2, $lr tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr - t2IT 0, 2, implicit-def $itstate, implicit $cpsr + t2IT 0, 2, implicit-def $itstate renamable $r0 = t2MOVi16 32767, 0, $cpsr, implicit killed $r0, implicit $itstate renamable $r0 = tSXTH killed renamable $r0, 0, $cpsr, implicit killed $r0, implicit $itstate tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-liveout-lsr-shift.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-liveout-lsr-shift.mir index 7f9ff11..109547e 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-liveout-lsr-shift.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-liveout-lsr-shift.mir @@ -115,7 +115,7 @@ body: | ; CHECK: successors: %bb.1(0x80000000) ; CHECK: liveins: $lr, $r0, $r1, $r2 ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 0, 2, implicit-def $itstate, implicit $cpsr + ; CHECK: t2IT 0, 2, implicit-def $itstate ; CHECK: renamable $r0 = t2MOVi16 32767, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate ; CHECK: renamable $r0 = tSXTH killed renamable $r0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate ; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate @@ -162,7 +162,7 @@ body: | liveins: $r0, $r1, $r2, $lr tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr - t2IT 0, 2, implicit-def $itstate, implicit $cpsr + t2IT 0, 2, implicit-def $itstate renamable $r0 = t2MOVi16 32767, 0, $cpsr, implicit killed $r0, implicit $itstate renamable $r0 = tSXTH killed renamable $r0, 0, $cpsr, implicit killed $r0, implicit $itstate tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-opcode-liveout.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-opcode-liveout.mir index 2e5e855..08e9524 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-opcode-liveout.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-opcode-liveout.mir @@ -117,7 +117,7 @@ body: | ; CHECK: successors: %bb.1(0x80000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 0, 4, implicit-def $itstate, implicit $cpsr + ; CHECK: t2IT 0, 4, implicit-def $itstate ; CHECK: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate ; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp @@ -161,7 +161,7 @@ body: | liveins: $r0, $r1, $r2, $lr, $r7 tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr - t2IT 0, 4, implicit-def $itstate, implicit $cpsr + t2IT 0, 4, implicit-def $itstate renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-operand-liveout.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-operand-liveout.mir index 1422a8a..bc5c190 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-operand-liveout.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-operand-liveout.mir @@ -109,7 +109,7 @@ body: | ; CHECK: successors: %bb.1(0x80000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 0, 4, implicit-def $itstate, implicit $cpsr + ; CHECK: t2IT 0, 4, implicit-def $itstate ; CHECK: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate ; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp @@ -149,7 +149,7 @@ body: | liveins: $r0, $r1, $r2, $lr, $r7 tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr - t2IT 0, 4, implicit-def $itstate, implicit $cpsr + t2IT 0, 4, implicit-def $itstate renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp diff --git a/llvm/test/CodeGen/Thumb2/constant-islands-cbz.mir b/llvm/test/CodeGen/Thumb2/constant-islands-cbz.mir index 690f27d..bc2b550 100644 --- a/llvm/test/CodeGen/Thumb2/constant-islands-cbz.mir +++ b/llvm/test/CodeGen/Thumb2/constant-islands-cbz.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=thumbv7m-none-eabi -run-pass=arm-cp-islands -o - %s --verify-machineinstrs | FileCheck %s +# RUN: llc -mtriple=thumbv7m-none-eabi -run-pass=arm-cp-islands -o - %s | FileCheck %s --- | define i32* @test_simple(i32* %x, i32 %y) { ret i32* %x } @@ -315,7 +315,7 @@ body: | liveins: $r0, $r1 tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr - t2IT 0, 8, implicit-def $itstate, implicit $cpsr + t2IT 0, 8, implicit-def $itstate renamable $r1 = t2ADDri killed renamable $r1, 1, 1, $cpsr, $noreg, implicit killed $itstate t2Bcc %bb.1, 0, killed $cpsr diff --git a/llvm/test/CodeGen/Thumb2/t2-teq-reduce.mir b/llvm/test/CodeGen/Thumb2/t2-teq-reduce.mir index 287b6a0..d0bcc66 100644 --- a/llvm/test/CodeGen/Thumb2/t2-teq-reduce.mir +++ b/llvm/test/CodeGen/Thumb2/t2-teq-reduce.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -run-pass=t2-reduce-size %s -o - --verify-machineinstrs | FileCheck %s +# RUN: llc -run-pass=t2-reduce-size %s -o - | FileCheck %s --- | target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" @@ -145,7 +145,7 @@ body: | renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.next.i.14) tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr BUNDLE implicit-def dead $itstate, implicit killed $cpsr, implicit $r0 { - t2IT 0, 8, implicit-def $itstate, implicit $cpsr + t2IT 0, 8, implicit-def $itstate tBX_RET 0, killed $cpsr, implicit $r0, implicit internal killed $itstate } @@ -165,7 +165,7 @@ body: | renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.next.i2) tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr BUNDLE implicit-def dead $itstate, implicit-def dead $r2, implicit-def $cpsr, implicit $r0, implicit killed $cpsr, implicit $r1 { - t2IT 1, 30, implicit-def $itstate, implicit $cpsr + t2IT 1, 30, implicit-def $itstate renamable $r2 = tLDRi renamable $r0, 1, 1, $cpsr, implicit internal $itstate :: (load 4 from %ir.info.i.1) renamable $r2 = tLDRHi internal killed renamable $r2, 0, 1, $cpsr, implicit internal killed $r2, implicit internal $itstate :: (load 2 from %ir.data16.i.13) t2TEQrr internal killed renamable $r2, renamable $r1, 1, killed $cpsr, implicit-def $cpsr, implicit internal killed $itstate -- 2.7.4