From 9628d61aa0d5fe3fd3e196a55cd51a8e5bbc1572 Mon Sep 17 00:00:00 2001 From: uros Date: Thu, 16 Dec 2004 09:29:57 +0000 Subject: [PATCH] * config/i386/i386.md (sqrt{s,d}f2_1, sqrt{s,d}f2_1_sse_only, sqrt{s,d}f2_i387): Unify enable constraint with respect to TARGET_SSE, TARGET_SSE2, TARGET_USE_FANCY_MATH_387, TARGET_SSE_MATH and TARGET_MIX_SSE_I387. (sqrt{s,d}f2_1): Rename to *sqrt{s,d}f2_mixed. (sqrt{s,d}f2_1_sse_only): Rename to *sqrt{s,d}f2_sse. (sqrt{s,d}f2_i387): Rename to *sqrt{s,d}f2_i387. (*sqrtextendsfdf2): Also enable for TARGET_MIX_SSE_I387. (*sqrtextend?f?f2): Rename to *sqrtextendsfdf2_i387. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@92247 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 12 ++++++++++++ gcc/config/i386/i386.md | 45 ++++++++++++++++++++------------------------- 2 files changed, 32 insertions(+), 25 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0cda2c6..31d471f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,17 @@ 2004-12-16 Uros Bizjak + * config/i386/i386.md (sqrt{s,d}f2_1, sqrt{s,d}f2_1_sse_only, + sqrt{s,d}f2_i387): Unify enable constraint with respect to + TARGET_SSE, TARGET_SSE2, TARGET_USE_FANCY_MATH_387, + TARGET_SSE_MATH and TARGET_MIX_SSE_I387. + (sqrt{s,d}f2_1): Rename to *sqrt{s,d}f2_mixed. + (sqrt{s,d}f2_1_sse_only): Rename to *sqrt{s,d}f2_sse. + (sqrt{s,d}f2_i387): Rename to *sqrt{s,d}f2_i387. + (*sqrtextendsfdf2): Also enable for TARGET_MIX_SSE_I387. + (*sqrtextend?f?f2): Rename to *sqrtextendsfdf2_i387. + +2004-12-16 Uros Bizjak + * config/i386/i386.md (*fop_?f_comm_{,sse,nosse}, *fop_?f_1_{,sse,nosse}, *fop_{d,x}f_{2,3,4,5,6}): Unify enable constraint with respect to TARGET_80387, TARGET_SSE, TARGET_SSE2, diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index b98159f..d5f5a86 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -14647,11 +14647,10 @@ operands[1] = force_reg (SFmode, operands[1]); }) -(define_insn "sqrtsf2_1" +(define_insn "*sqrtsf2_mixed" [(set (match_operand:SF 0 "register_operand" "=f#x,x#f") (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "0#x,xm#f")))] - "TARGET_USE_FANCY_MATH_387 - && (TARGET_SSE_MATH && TARGET_MIX_SSE_I387)" + "TARGET_USE_FANCY_MATH_387 && TARGET_MIX_SSE_I387" "@ fsqrt sqrtss\t{%1, %0|%0, %1}" @@ -14659,20 +14658,19 @@ (set_attr "mode" "SF,SF") (set_attr "athlon_decode" "direct,*")]) -(define_insn "sqrtsf2_1_sse_only" +(define_insn "*sqrtsf2_sse" [(set (match_operand:SF 0 "register_operand" "=x") (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "xm")))] - "TARGET_SSE_MATH && (!TARGET_80387 || !TARGET_MIX_SSE_I387)" + "TARGET_SSE_MATH" "sqrtss\t{%1, %0|%0, %1}" [(set_attr "type" "sse") (set_attr "mode" "SF") (set_attr "athlon_decode" "*")]) -(define_insn "sqrtsf2_i387" +(define_insn "*sqrtsf2_i387" [(set (match_operand:SF 0 "register_operand" "=f") (sqrt:SF (match_operand:SF 1 "register_operand" "0")))] - "TARGET_USE_FANCY_MATH_387 - && !TARGET_SSE_MATH" + "TARGET_USE_FANCY_MATH_387" "fsqrt" [(set_attr "type" "fpspc") (set_attr "mode" "SF") @@ -14681,18 +14679,16 @@ (define_expand "sqrtdf2" [(set (match_operand:DF 0 "register_operand" "") (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "")))] - "TARGET_USE_FANCY_MATH_387 - || (TARGET_SSE2 && TARGET_SSE_MATH)" + "TARGET_USE_FANCY_MATH_387 || (TARGET_SSE2 && TARGET_SSE_MATH)" { - if (!TARGET_SSE2 || !TARGET_SSE_MATH) + if (!(TARGET_SSE2 && TARGET_SSE_MATH)) operands[1] = force_reg (DFmode, operands[1]); }) -(define_insn "sqrtdf2_1" +(define_insn "*sqrtdf2_mixed" [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f") (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "0#Y,Ym#f")))] - "TARGET_USE_FANCY_MATH_387 - && (TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387)" + "TARGET_USE_FANCY_MATH_387 && TARGET_SSE2 && TARGET_MIX_SSE_I387" "@ fsqrt sqrtsd\t{%1, %0|%0, %1}" @@ -14700,31 +14696,30 @@ (set_attr "mode" "DF,DF") (set_attr "athlon_decode" "direct,*")]) -(define_insn "sqrtdf2_1_sse_only" +(define_insn "*sqrtdf2_sse" [(set (match_operand:DF 0 "register_operand" "=Y") (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "Ym")))] - "TARGET_SSE2 && TARGET_SSE_MATH && (!TARGET_80387 || !TARGET_MIX_SSE_I387)" + "TARGET_SSE2 && TARGET_SSE_MATH" "sqrtsd\t{%1, %0|%0, %1}" [(set_attr "type" "sse") (set_attr "mode" "DF") (set_attr "athlon_decode" "*")]) -(define_insn "sqrtdf2_i387" +(define_insn "*sqrtdf2_i387" [(set (match_operand:DF 0 "register_operand" "=f") (sqrt:DF (match_operand:DF 1 "register_operand" "0")))] - "TARGET_USE_FANCY_MATH_387 - && (!TARGET_SSE2 || !TARGET_SSE_MATH)" + "TARGET_USE_FANCY_MATH_387" "fsqrt" [(set_attr "type" "fpspc") (set_attr "mode" "DF") (set_attr "athlon_decode" "direct")]) -(define_insn "*sqrtextendsfdf2" +(define_insn "*sqrtextendsfdf2_i387" [(set (match_operand:DF 0 "register_operand" "=f") (sqrt:DF (float_extend:DF (match_operand:SF 1 "register_operand" "0"))))] "TARGET_USE_FANCY_MATH_387 - && !(TARGET_SSE2 && TARGET_SSE_MATH)" + && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)" "fsqrt" [(set_attr "type" "fpspc") (set_attr "mode" "DF") @@ -14740,20 +14735,20 @@ (set_attr "mode" "XF") (set_attr "athlon_decode" "direct")]) -(define_insn "*sqrtextenddfxf2" +(define_insn "*sqrtextendsfxf2_i387" [(set (match_operand:XF 0 "register_operand" "=f") (sqrt:XF (float_extend:XF - (match_operand:DF 1 "register_operand" "0"))))] + (match_operand:SF 1 "register_operand" "0"))))] "TARGET_USE_FANCY_MATH_387" "fsqrt" [(set_attr "type" "fpspc") (set_attr "mode" "XF") (set_attr "athlon_decode" "direct")]) -(define_insn "*sqrtextendsfxf2" +(define_insn "*sqrtextenddfxf2_i387" [(set (match_operand:XF 0 "register_operand" "=f") (sqrt:XF (float_extend:XF - (match_operand:SF 1 "register_operand" "0"))))] + (match_operand:DF 1 "register_operand" "0"))))] "TARGET_USE_FANCY_MATH_387" "fsqrt" [(set_attr "type" "fpspc") -- 2.7.4