From 960ad8c07a9d27d8c4d0487115efde7143430c1c Mon Sep 17 00:00:00 2001 From: Lei Yang Date: Wed, 9 Oct 2019 19:35:37 +0800 Subject: [PATCH] hdmirx: keep SCDC_EN on [1/1] PD#SWPL-14701 Problem: AppleTV box always read SCDC status whether EDID support 2.0 or not Solution: 1.Cannot disable scdc function at hdmi1.4 mode. otherwise appletv didnot sent valid data 2.remove oscillator mode in algorithm of PHY pll Verify: 962X2 Change-Id: I6b87c8268073e52f2393844989fcf50057a99ace Signed-off-by: Lei Yang --- .../amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.c | 8 ---- .../amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h | 2 +- drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c | 49 +++++++++------------- 3 files changed, 20 insertions(+), 39 deletions(-) diff --git a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.c b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.c index 8d5b1d8..af5f20f0 100644 --- a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.c +++ b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.c @@ -2438,14 +2438,6 @@ static int hdmirx_probe(struct platform_device *pdev) rx.arc_port = 0x1; rx_pr("not find arc_port, portB by default\n"); } - ret = of_property_read_u32(pdev->dev.of_node, - "scdc_force_en", - &scdc_force_en); - if (ret) { - /* enable scdc accroding to edid version */ - scdc_force_en = 0; - rx_pr("not find scdc_force_en, disable by default\n"); - } ret = of_reserved_mem_device_init(&(pdev->dev)); if (ret != 0) diff --git a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h index 3627135..7d26172 100644 --- a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h +++ b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h @@ -34,7 +34,7 @@ #include "hdmi_rx_edid.h" -#define RX_VER0 "ver.2019-09-27" +#define RX_VER0 "ver.2019-10-09" /* * * diff --git a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c index c1fc51b..3c6320a 100644 --- a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c +++ b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c @@ -101,7 +101,7 @@ int pll_rst_max = 5; /* cdr lock threshold */ int cdr_lock_level; int clock_lock_th = 2; -int scdc_force_en; +int scdc_force_en = 1; /* for hdcp_hpd debug, disable by default */ bool hdcp_hpd_ctrl_en; @@ -3863,7 +3863,6 @@ void aml_phy_pll_setting(void) uint32_t data, data2; uint32_t cableclk = rx.phy.cable_clk / KHz; int pll_rst_cnt = 0; - int m_div; od_div = apll_tab[bw].od_div; od = apll_tab[bw].od; @@ -3883,17 +3882,19 @@ void aml_phy_pll_setting(void) if (is_tl1_former()) od2 += 1; do { - if ((vco_clk > (3000 * KHz)) && (vco_clk < (4800 * KHz)) && - (M <= 80)) { - data2 = 0x300b8f30 | od2; - m_div = 2; - } else { - data2 = 0x300d8f30 | od2; - m_div = 1; - } - + /*cntl0 M <7:0> N<14:10>*/ + data = 0x00090400 & 0xffff8300; + data |= M; + data |= (N << 10); + wr_reg_hhi(HHI_HDMIRX_APLL_CNTL0, data | 0x20000000); + udelay(5); + wr_reg_hhi(HHI_HDMIRX_APLL_CNTL0, data | 0x30000000); + udelay(5); wr_reg_hhi(HHI_HDMIRX_APLL_CNTL1, 0x00000000); - wr_reg_hhi(HHI_HDMIRX_APLL_CNTL2, 0x0000503c); + udelay(5); + wr_reg_hhi(HHI_HDMIRX_APLL_CNTL2, 0x00001118); + udelay(5); + data2 = 0x10058f30 | od2; wr_reg_hhi(HHI_HDMIRX_APLL_CNTL3, data2); if (is_tl1_former()) data2 = 0x000100c0; @@ -3901,27 +3902,15 @@ void aml_phy_pll_setting(void) data2 = 0x080130c0; data2 |= (od << 24); wr_reg_hhi(HHI_HDMIRX_APLL_CNTL4, data2); - udelay(1); - /*cntl0 M <7:0> N<14:10>*/ - data = 0x00090000; - data |= M * m_div; - data |= (N << 10); - wr_reg_hhi(HHI_HDMIRX_APLL_CNTL0, data | 0x20000000); - wr_reg_hhi(HHI_HDMIRX_APLL_CNTL0, data | 0x30000000); - udelay(50); + udelay(5); + /*apll_vctrl_mon_en*/ wr_reg_hhi(HHI_HDMIRX_APLL_CNTL4, data2 | 0x00800000); - udelay(50); + udelay(5); wr_reg_hhi(HHI_HDMIRX_APLL_CNTL0, data | 0x34000000); - udelay(50); - if (m_div == 2) { - m_div = 1; - data &= 0xffffff00; - data |= M * m_div; - wr_reg_hhi(HHI_HDMIRX_APLL_CNTL0, data | 0x34000000); - udelay(50); - } - data &= 0xdfffffff; + udelay(5); wr_reg_hhi(HHI_HDMIRX_APLL_CNTL0, data | 0x14000000); + udelay(5); + /* bit'5: force lock bit'2: improve phy ldo voltage */ wr_reg_hhi(HHI_HDMIRX_APLL_CNTL2, 0x0000303c); -- 2.7.4