From 95f79553849cfb936f8c1e8d453b5a8b73db462c Mon Sep 17 00:00:00 2001 From: Dylan Hung Date: Tue, 21 Feb 2023 21:01:10 +0800 Subject: [PATCH] clk: ast2600: Keep PLL power on According to the PLL vendor, we should keep the PLL power on, so we shouldn't toggle the power-down bit during PLL initialization. Signed-off-by: Dylan Hung Reviewed-by: Joel Stanley --- drivers/clk/aspeed/clk_ast2600.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/clk/aspeed/clk_ast2600.c b/drivers/clk/aspeed/clk_ast2600.c index 0df1dc3..e5ada5b 100644 --- a/drivers/clk/aspeed/clk_ast2600.c +++ b/drivers/clk/aspeed/clk_ast2600.c @@ -538,7 +538,7 @@ static uint32_t ast2600_configure_pll(struct ast2600_scu *scu, } p_cfg->reg.b.bypass = 0; - p_cfg->reg.b.off = 1; + p_cfg->reg.b.off = 0; p_cfg->reg.b.reset = 1; reg = readl(addr); @@ -549,7 +549,6 @@ static uint32_t ast2600_configure_pll(struct ast2600_scu *scu, /* write extend parameter */ writel(p_cfg->ext_reg, addr_ext); udelay(100); - p_cfg->reg.b.off = 0; p_cfg->reg.b.reset = 0; reg &= ~GENMASK(25, 0); reg |= p_cfg->reg.w; -- 2.7.4