From 95f3bccd30ad15ca20f818d429ca233590dce242 Mon Sep 17 00:00:00 2001 From: Egor Bogatov Date: Sat, 29 Jul 2023 21:04:01 +0200 Subject: [PATCH] JIT: Don't use addressing modes for volatile loads for gc types (#70794) --- src/coreclr/jit/gcinfo.cpp | 3 ++- src/coreclr/jit/lower.cpp | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/coreclr/jit/gcinfo.cpp b/src/coreclr/jit/gcinfo.cpp index 613f76c..bd2f924 100644 --- a/src/coreclr/jit/gcinfo.cpp +++ b/src/coreclr/jit/gcinfo.cpp @@ -316,9 +316,10 @@ GCInfo::WriteBarrierForm GCInfo::gcWriteBarrierFormFromTargetAddress(GenTree* tg GenTree* addOp2 = tgtAddr->AsOp()->gtGetOp2(); var_types addOp1Type = addOp1->TypeGet(); var_types addOp2Type = addOp2->TypeGet(); + if (addOp1Type == TYP_BYREF || addOp1Type == TYP_REF) { - assert(addOp2Type != TYP_BYREF && addOp2Type != TYP_REF); + assert(((addOp2Type != TYP_BYREF) || (addOp2->OperIs(GT_CNS_INT))) && (addOp2Type != TYP_REF)); tgtAddr = addOp1; simplifiedExpr = true; } diff --git a/src/coreclr/jit/lower.cpp b/src/coreclr/jit/lower.cpp index 157fda6..81df694 100644 --- a/src/coreclr/jit/lower.cpp +++ b/src/coreclr/jit/lower.cpp @@ -6033,7 +6033,7 @@ bool Lowering::TryCreateAddrMode(GenTree* addr, bool isContainable, GenTree* par } #ifdef TARGET_ARM64 - if (parent->OperIsIndir() && parent->AsIndir()->IsVolatile() && !varTypeIsGC(addr)) + if (parent->OperIsIndir() && parent->AsIndir()->IsVolatile()) { // For Arm64 we avoid using LEA for volatile INDs // because we won't be able to use ldar/star -- 2.7.4