From 958eb4644393636a22d3dcb66c39c8f0718997c5 Mon Sep 17 00:00:00 2001 From: Andrey Turetskiy Date: Fri, 1 Apr 2016 10:16:15 +0000 Subject: [PATCH] [X86] Introduce Lakemont CPU. Add a new Intel MCU CPU Lakemont, which doesn't support X87. Differential Revision: http://reviews.llvm.org/D18650 llvm-svn: 265128 --- llvm/lib/Target/X86/X86.td | 3 +++ llvm/test/CodeGen/X86/lakemont.ll | 9 +++++++++ 2 files changed, 12 insertions(+) create mode 100644 llvm/test/CodeGen/X86/lakemont.ll diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td index 962a3dd..1699330 100644 --- a/llvm/lib/Target/X86/X86.td +++ b/llvm/lib/Target/X86/X86.td @@ -283,6 +283,9 @@ def : Proc<"pentium4", [FeatureX87, FeatureSlowUAMem16, FeatureMMX, def : Proc<"pentium4m", [FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE2, FeatureFXSR, FeatureSlowBTMem]>; +// Intel Quark. +def : Proc<"lakemont", []>; + // Intel Core Duo. def : ProcessorModel<"yonah", SandyBridgeModel, [FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE3, diff --git a/llvm/test/CodeGen/X86/lakemont.ll b/llvm/test/CodeGen/X86/lakemont.ll new file mode 100644 index 0000000..ddd2452 --- /dev/null +++ b/llvm/test/CodeGen/X86/lakemont.ll @@ -0,0 +1,9 @@ +; RUN: llc < %s -march=x86 -mcpu=lakemont | FileCheck %s + +; Make sure -mcpu=lakemont implies soft floats. +define float @test(float %a, float %b) nounwind readnone { +; CHECK-LABEL: test: +; CHECK: __addsf3 + %add = fadd float %a, %b + ret float %add +} -- 2.7.4