From 9584959123b0453cf5313722357e3abb9f736aa7 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Thu, 8 May 2014 16:44:37 -0700 Subject: [PATCH] i965: Fix GPU hangs on Broadwell in shaders with some control flow. MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit According to the documentation, we need to set the source 0 register type to IMM for flow control instructions that have both JIP and UIP. Fixes GPU hangs in approximately 10 Piglit tests, 5 es3conform tests, Unigine Crypt, a WebGL raytracer demo, and several Steam titles. Cc: "10.2" Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75478 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75878 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76939 Signed-off-by: Kenneth Graunke Tested-by: Topi Pohjolainen Tested-by: Kristian Høgsberg Reviewed-by: Jordan Justen Reviewed-by: Matt Turner --- src/mesa/drivers/dri/i965/gen8_generator.cpp | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen8_generator.cpp b/src/mesa/drivers/dri/i965/gen8_generator.cpp index dd434a7..faca9c0 100644 --- a/src/mesa/drivers/dri/i965/gen8_generator.cpp +++ b/src/mesa/drivers/dri/i965/gen8_generator.cpp @@ -422,6 +422,7 @@ gen8_generator::IF(unsigned predicate) { gen8_instruction *inst = next_inst(BRW_OPCODE_IF); gen8_set_dst(brw, inst, vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_D))); + gen8_set_src0(brw, inst, brw_imm_d(0)); gen8_set_exec_size(inst, default_state.exec_size); gen8_set_pred_control(inst, predicate); gen8_set_mask_control(inst, BRW_MASK_ENABLE); @@ -435,6 +436,7 @@ gen8_generator::ELSE() { gen8_instruction *inst = next_inst(BRW_OPCODE_ELSE); gen8_set_dst(brw, inst, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); + gen8_set_src0(brw, inst, brw_imm_d(0)); gen8_set_mask_control(inst, BRW_MASK_ENABLE); push_if_stack(inst); return inst; @@ -456,6 +458,7 @@ gen8_generator::ENDIF() gen8_instruction *endif_inst = next_inst(BRW_OPCODE_ENDIF); gen8_set_mask_control(endif_inst, BRW_MASK_ENABLE); + gen8_set_src0(brw, endif_inst, brw_imm_d(0)); patch_IF_ELSE(if_inst, else_inst, endif_inst); return endif_inst; @@ -577,8 +580,7 @@ gen8_generator::BREAK() { gen8_instruction *inst = next_inst(BRW_OPCODE_BREAK); gen8_set_dst(brw, inst, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); - gen8_set_src0(brw, inst, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); - gen8_set_src1(brw, inst, brw_imm_d(0)); + gen8_set_src0(brw, inst, brw_imm_d(0)); gen8_set_exec_size(inst, default_state.exec_size); return inst; } @@ -588,8 +590,7 @@ gen8_generator::CONTINUE() { gen8_instruction *inst = next_inst(BRW_OPCODE_CONTINUE); gen8_set_dst(brw, inst, brw_ip_reg()); - gen8_set_src0(brw, inst, brw_ip_reg()); - gen8_set_src1(brw, inst, brw_imm_d(0)); + gen8_set_src0(brw, inst, brw_imm_d(0)); gen8_set_exec_size(inst, default_state.exec_size); return inst; } @@ -601,8 +602,7 @@ gen8_generator::WHILE() gen8_instruction *while_inst = next_inst(BRW_OPCODE_WHILE); gen8_set_dst(brw, while_inst, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); - gen8_set_src0(brw, while_inst, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); - gen8_set_src1(brw, while_inst, brw_imm_ud(0)); + gen8_set_src0(brw, while_inst, brw_imm_d(0)); gen8_set_jip(while_inst, 16 * (do_inst - while_inst)); gen8_set_exec_size(while_inst, default_state.exec_size); @@ -614,7 +614,7 @@ gen8_generator::HALT() { gen8_instruction *inst = next_inst(BRW_OPCODE_HALT); gen8_set_dst(brw, inst, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); - gen8_set_src0(brw, inst, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); + gen8_set_src0(brw, inst, brw_imm_d(0)); gen8_set_exec_size(inst, default_state.exec_size); gen8_set_mask_control(inst, BRW_MASK_DISABLE); return inst; -- 2.7.4