From 956ee797955c852e4055194a82c78a3ba3519128 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Fri, 30 Mar 2018 22:22:31 +0000 Subject: [PATCH] Fix a bunch of typoes. NFC llvm-svn: 328907 --- llvm/lib/Analysis/TargetLibraryInfo.cpp | 2 +- llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 2 +- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 2 +- llvm/lib/CodeGen/StackColoring.cpp | 2 +- llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp | 2 +- llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp | 2 +- llvm/lib/Target/Hexagon/HexagonISelLowering.cpp | 2 +- llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp | 8 ++++---- llvm/lib/Target/Mips/MipsInstrInfo.cpp | 2 +- llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp | 3 +-- llvm/lib/Transforms/Scalar/ADCE.cpp | 4 ++-- llvm/lib/Transforms/Scalar/LICM.cpp | 2 +- llvm/utils/TableGen/CodeGenDAGPatterns.cpp | 2 +- llvm/utils/TableGen/X86FoldTablesEmitter.cpp | 2 +- 14 files changed, 18 insertions(+), 19 deletions(-) diff --git a/llvm/lib/Analysis/TargetLibraryInfo.cpp b/llvm/lib/Analysis/TargetLibraryInfo.cpp index 8b9f2a2..87b4051 100644 --- a/llvm/lib/Analysis/TargetLibraryInfo.cpp +++ b/llvm/lib/Analysis/TargetLibraryInfo.cpp @@ -245,7 +245,7 @@ static void initialize(TargetLibraryInfoImpl &TLI, const Triple &T, TLI.setUnavailable(LibFunc_tanhf); } - // Win32 does *not* provide provide these functions, but they are + // Win32 does *not* provide these functions, but they are // generally available on POSIX-compliant systems: TLI.setUnavailable(LibFunc_access); TLI.setUnavailable(LibFunc_bcmp); diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index bb01952b..4994115 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -9677,7 +9677,7 @@ void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond, }); // Rearrange the case blocks so that the last one falls through if possible - // without without changing the order of probabilities. + // without changing the order of probabilities. for (CaseClusterIt I = W.LastCluster; I > W.FirstCluster; ) { --I; if (I->Prob > W.LastCluster->Prob) diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index e6e07e8..c40b443 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -2300,7 +2300,7 @@ bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, // If Root use can somehow reach N through a path that that doesn't contain // U then folding N would create a cycle. e.g. In the following - // diagram, Root can reach N through X. If N is folded into into Root, then + // diagram, Root can reach N through X. If N is folded into Root, then // X is both a predecessor and a successor of U. // // [N*] // diff --git a/llvm/lib/CodeGen/StackColoring.cpp b/llvm/lib/CodeGen/StackColoring.cpp index 9d1bd30..8a8fc70 100644 --- a/llvm/lib/CodeGen/StackColoring.cpp +++ b/llvm/lib/CodeGen/StackColoring.cpp @@ -993,7 +993,7 @@ void StackColoring::remapInstructions(DenseMap &SlotRemap) { // the calculated range then it means that the alloca usage moved // outside of the lifetime markers, or that the user has a bug. // NOTE: Alloca address calculations which happen outside the lifetime - // zone are are okay, despite the fact that we don't have a good way + // zone are okay, despite the fact that we don't have a good way // for validating all of the usages of the calculation. #ifndef NDEBUG bool TouchesMemory = I.mayLoad() || I.mayStore(); diff --git a/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp b/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp index 1c3a246..fdf6423 100644 --- a/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp +++ b/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp @@ -609,7 +609,7 @@ void BPFDAGToDAGISel::PreprocessTrunc(SDNode *Node, // %2 = PHI %0, <%bb.1>, %1, <%bb.3> // Trace each incoming definition, e.g., (%0, %bb.1) and (%1, %bb.3) // The AND operation can be removed if both %0 in %bb.1 and %1 in - // %bb.3 are defined with with a load matching the MaskN. + // %bb.3 are defined with a load matching the MaskN. DEBUG(dbgs() << "Check PHI Insn: "; MII->dump(); dbgs() << '\n'); unsigned PrevReg = -1; for (unsigned i = 0; i < MII->getNumOperands(); ++i) { diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp index 3758362..7eddf55 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp @@ -259,7 +259,7 @@ bool Coloring::color() { Colors[C] = ColorC; } - // Explicitly assign "None" all all uncolored nodes. + // Explicitly assign "None" to all uncolored nodes. for (unsigned I = 0; I != Order.size(); ++I) if (Colors.count(I) == 0) Colors[I] = ColorKind::None; diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp index 8c7b492..91af9e2 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -414,7 +414,7 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, VA.getLocVT().getStoreSizeInBits() >> 3); if (Flags.isByVal()) { // The argument is a struct passed by value. According to LLVM, "Arg" - // is is pointer. + // is a pointer. MemOpChains.push_back(CreateCopyOfByValArgument(Arg, MemAddr, Chain, Flags, DAG, dl)); } else { diff --git a/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp b/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp index 2608096..344652f 100644 --- a/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp +++ b/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp @@ -16,7 +16,7 @@ // The basic approach looks for sequence of predicated jump, compare instruciton // that genereates the predicate and, the feeder to the predicate. Once it finds -// all, it collapses compare and jump instruction into a new valu jump +// all, it collapses compare and jump instruction into a new value jump // intstructions. // //===----------------------------------------------------------------------===// @@ -159,7 +159,7 @@ static bool canBeFeederToNewValueJump(const HexagonInstrInfo *QII, } assert(HadDef); - // Make sure there there is no 'def' or 'use' of any of the uses of + // Make sure there is no 'def' or 'use' of any of the uses of // feeder insn between it's definition, this MI and jump, jmpInst // skipping compare, cmpInst. // Here's the example. @@ -287,8 +287,8 @@ static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII, if (cmpReg1 == cmpOp2) return false; - // Make sure that that second register is not from COPY - // At machine code level, we don't need this, but if we decide + // Make sure that the second register is not from COPY + // at machine code level, we don't need this, but if we decide // to move new value jump prior to RA, we would be needing this. MachineRegisterInfo &MRI = MF.getRegInfo(); if (secondReg && !TargetRegisterInfo::isPhysicalRegister(cmpOp2)) { diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.cpp b/llvm/lib/Target/Mips/MipsInstrInfo.cpp index 2e30d27..947d7e4 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.cpp +++ b/llvm/lib/Target/Mips/MipsInstrInfo.cpp @@ -598,7 +598,7 @@ bool MipsInstrInfo::verifyInstruction(const MachineInstr &MI, case Mips::DINS: return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 0, 32, 0, 32); case Mips::DINSM: - // The ISA spec has a subtle difference difference between dinsm and dextm + // The ISA spec has a subtle difference between dinsm and dextm // in that it says: // 2 <= size <= 64 for 'dinsm' but 'dextm' has 32 < size <= 64. // To make the bounds checks similar, the range 1 < size <= 64 is checked diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp index eea94b2..a469f0b 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp +++ b/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp @@ -663,8 +663,7 @@ protected: // instruction. CompactUnwindEncoding |= (SubtractInstrIdx & 0xFF) << 16; - // Encode any extra stack stack adjustments (done via push - // instructions). + // Encode any extra stack adjustments (done via push instructions). CompactUnwindEncoding |= (StackAdjust & 0x7) << 13; } diff --git a/llvm/lib/Transforms/Scalar/ADCE.cpp b/llvm/lib/Transforms/Scalar/ADCE.cpp index 1e683db..03a44849 100644 --- a/llvm/lib/Transforms/Scalar/ADCE.cpp +++ b/llvm/lib/Transforms/Scalar/ADCE.cpp @@ -174,8 +174,8 @@ class AggressiveDeadCodeElimination { /// marked live. void markLiveBranchesFromControlDependences(); - /// Remove instructions not marked live, return if any any instruction - /// was removed. + /// Remove instructions not marked live, return if any instruction was + /// removed. bool removeDeadInstructions(); /// Identify connected sections of the control flow graph which have diff --git a/llvm/lib/Transforms/Scalar/LICM.cpp b/llvm/lib/Transforms/Scalar/LICM.cpp index 414f3b7..b6e16ba 100644 --- a/llvm/lib/Transforms/Scalar/LICM.cpp +++ b/llvm/lib/Transforms/Scalar/LICM.cpp @@ -1335,7 +1335,7 @@ bool llvm::promoteLoopAccessesToScalars( // If a store dominates all exit blocks, it is safe to sink. // As explained above, if an exit block was executed, a dominating - // store must have been been executed at least once, so we are not + // store must have been executed at least once, so we are not // introducing stores on paths that did not have them. // Note that this only looks at explicit exit blocks. If we ever // start sinking stores into unwind edges (see above), this will break. diff --git a/llvm/utils/TableGen/CodeGenDAGPatterns.cpp b/llvm/utils/TableGen/CodeGenDAGPatterns.cpp index 493066e..23c04d9 100644 --- a/llvm/utils/TableGen/CodeGenDAGPatterns.cpp +++ b/llvm/utils/TableGen/CodeGenDAGPatterns.cpp @@ -2660,7 +2660,7 @@ TreePatternNode *TreePattern::ParseTreePattern(Init *TheInit, StringRef OpName){ // node (which is hard-coded to have either zero or one result). unsigned NumResults = GetNumNodeResults(Operator, CDP); - // If the operator is an intrinsic, then this is just syntactic sugar for for + // If the operator is an intrinsic, then this is just syntactic sugar for // (intrinsic_* , ..children..). Pick the right intrinsic node, and // convert the intrinsic name to a number. if (Operator->isSubClassOf("Intrinsic")) { diff --git a/llvm/utils/TableGen/X86FoldTablesEmitter.cpp b/llvm/utils/TableGen/X86FoldTablesEmitter.cpp index fc327c8..038efdc 100644 --- a/llvm/utils/TableGen/X86FoldTablesEmitter.cpp +++ b/llvm/utils/TableGen/X86FoldTablesEmitter.cpp @@ -551,7 +551,7 @@ void X86FoldTablesEmitter::updateTables(const CodeGenInstruction *RegInstr, } } else if (MemInSize == RegInSize + 1 && MemOutSize + 1 == RegOutSize) { // Store-Folding cases. - // If the memory form instruction performs performs a store, the *output* + // If the memory form instruction performs a store, the *output* // register of the register form instructions disappear and instead a // memory *input* operand appears in the memory form instruction. // For example: -- 2.7.4