From 95546b46ab62e8349346a0d0587eee8248dd4b2f Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Sat, 14 Feb 2015 02:55:57 +0000 Subject: [PATCH] R600/SI: Fix phys reg copies in SIFoldOperands llvm-svn: 229227 --- llvm/lib/Target/R600/SIFoldOperands.cpp | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/R600/SIFoldOperands.cpp b/llvm/lib/Target/R600/SIFoldOperands.cpp index 848638f..a1feeb4 100644 --- a/llvm/lib/Target/R600/SIFoldOperands.cpp +++ b/llvm/lib/Target/R600/SIFoldOperands.cpp @@ -210,7 +210,12 @@ bool SIFoldOperands::runOnMachineFunction(MachineFunction &MF) { APInt Imm; if (FoldingImm) { - const TargetRegisterClass *UseRC = MRI.getRegClass(UseOp.getReg()); + unsigned UseReg = UseOp.getReg(); + const TargetRegisterClass *UseRC + = TargetRegisterInfo::isVirtualRegister(UseReg) ? + MRI.getRegClass(UseReg) : + TRI.getRegClass(UseReg); + Imm = APInt(64, OpToFold.getImm()); // Split 64-bit constants into 32-bits for folding. @@ -229,8 +234,13 @@ bool SIFoldOperands::runOnMachineFunction(MachineFunction &MF) { // In order to fold immediates into copies, we need to change the // copy to a MOV. if (UseMI->getOpcode() == AMDGPU::COPY) { - unsigned MovOp = TII->getMovOpcode( - MRI.getRegClass(UseMI->getOperand(0).getReg())); + unsigned DestReg = UseMI->getOperand(0).getReg(); + const TargetRegisterClass *DestRC + = TargetRegisterInfo::isVirtualRegister(DestReg) ? + MRI.getRegClass(DestReg) : + TRI.getRegClass(DestReg); + + unsigned MovOp = TII->getMovOpcode(DestRC); if (MovOp == AMDGPU::COPY) continue; -- 2.7.4