From 94ebe625c3c8c604014d1220cce8df8c9e7a7207 Mon Sep 17 00:00:00 2001 From: vmakarov Date: Wed, 13 Jan 1999 15:28:22 +0000 Subject: [PATCH] Thu Jan 11 18:37:50 1999 Vladimir N. Makarov * invoke.texi (-mcpu=740, -mcpu=750): New options. (-m(no-)multiple, -m(no-)string): Describe cases for PPC740 & PPC750. 1999-01-11 Michael Meissner * config/rs6000/rs6000.h ({ASM,CPP}_CPU_SPEC): Add support for all machines supported with -mcpu=xxx. (processor_type): Add PROCESSOR_PPC750. (ADJUST_PRIORITY): Call rs6000_adjust_priority. (RTX_COSTS): Supply costs for 750 multiply/divide operations. (rs6000_adjust_priority): Add declaration. * config/rs6000/rs6000.c (rs6000_override_options): -mcpu={750,740} now sets the processor type as 750, not 603. Allow -mmultiple and -mstring on little endian 750 systems. (rs6000_adjust_priority): Stub for now. (get_issue_rate): The PowerPC 750 can issue 2 instructions/cycle. * config/rs6000/rs6000.md (function/cpu attributes): Add initial ppc750 support. * config/rs6000/sysv4.h (STRICT_ALIGNMENT): Don't force strict alignment if little endian. (CC1_SPEC): Pass -mstrict-align if little endian, and not overridden. (CC1_ENDIAN_{LITTLE,BIG,DEFAULT}_SPEC): Endian specific configs. (SUBTARGET_EXTRA_SPECS): Add cc1 endian specs. * config/rs6000/{sysv4,eabi}le.h (CC1_ENDIAN_DEFAULT_SPEC): Override, default is little endian. * config/rs6000/t-ppcgas (MULTILIB_*): Delete obsolete Solaris multilibs. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@24654 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 87 ++++++++++++++++++------------------------ gcc/config/rs6000/eabile.h | 3 ++ gcc/config/rs6000/rs6000.c | 93 +++++++++++++++++++++++++++++++++++++-------- gcc/config/rs6000/rs6000.h | 61 +++++++++++++++++++---------- gcc/config/rs6000/rs6000.md | 76 +++++++++++++++++++++--------------- gcc/config/rs6000/sysv4.h | 45 ++++++++++++++++------ gcc/config/rs6000/sysv4le.h | 3 ++ gcc/config/rs6000/t-ppcgas | 9 ++--- gcc/invoke.texi | 31 ++++++++------- 9 files changed, 260 insertions(+), 148 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a11bfc0..b36115d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,53 +1,3 @@ -Wed Jan 13 16:16:44 1999 Catherine Moore - - * config/arm.c (output_func_epilogue): Check TARGET_ABORT_NORETURN - before generating a call to abort for volatile functions. - * config/arm.h (ARM_FLAG_ABORT_NORETURN): Define. - (TARGET_ABORT_NORETURN): Define. - (abort-on-noreturn): New option. - -Wed Jan 13 13:30:08 1999 Kaveh R. Ghazi - - * cccp.c (xstrdup): Renamed from `savestring'. All callers changed. - Remove prototype which we get from libiberty.h. - - * collect2.c (xstrdup): Likewise. - - * genextract.c (xstrdup): Likewise for `copystr'. - (mybzero): Remove it and use `memset' instead. - - * genoutput.c (mybcopy, mybzero): Remove these. All callers changed - to use `memcpy' and `memset' instead. - - * genrecog.c (xstrdup): Renamed from `copystr'. All callers - changed. Remove prototype. - (mybcopy, mybzero): Remove these and use memcpy/memset. - -Wed Jan 13 00:59:04 1999 Jeffrey A Law (law@cygnus.com) - - * mips.h (LOAD_EXTEND_OP): Correct for SImode and CCmode moves when - generating code for TARGET_64BIT. - -Tue Jan 12 14:05:37 1999 David Edelsohn - - * rs6000.c (print_operand, cases 'm' and 'M'): Do not depend on - HOST_WIDE_INT word-size. - (rs6000_stack_info): Remove redundant alignment of fpmem. - -Tue Jan 12 14:05:37 1999 Richard Henderson - - * rs6000.c (short_cint_operand): Remove CONSTANT_P_RTX handling. - (u_short_cint_operand, reg_or_cint_operand, logical_operand): Likewise. - (input_operand): Adjust CONSTANT_P_RTX handling. - * rs6000.h (PREDICATE_CODES): Remove CONSTANT_P_RTX references. - * rs6000.md (movsi): Adjust CONSTANT_P_RTX handling. - (movhi, movqi): Remove CONSANT_P_RTX handling. - (movdi): Adjust CONSTANT_P_RTX handling. - -Tue Jan 12 10:23:24 1999 Stan Cox - - * mips.md (call_value_internal3c): New pattern for -mips16 -mlong-calls. - 1999-01-12 Manfred Hollstein * m68k/mot3300.h (ADD_MISSING_POSIX, ADD_MISSING_XOPEN): Define to @@ -107,6 +57,43 @@ Mon Jan 11 22:36:01 1999 Richard Henderson * graph.c, haifa-sched.c, local-alloc.c, regclass.c: Likewise. * regmove.c, reload1.c, reorg.c, sched.c: Likewise. +Thu Jan 11 18:37:50 1999 Vladimir N. Makarov + + * invoke.texi (-mcpu=740, -mcpu=750): New options. + (-m(no-)multiple, -m(no-)string): Describe cases for PPC740 & + PPC750. + +1999-01-11 Michael Meissner + + * config/rs6000/rs6000.h ({ASM,CPP}_CPU_SPEC): Add support for all + machines supported with -mcpu=xxx. + (processor_type): Add PROCESSOR_PPC750. + (ADJUST_PRIORITY): Call rs6000_adjust_priority. + (RTX_COSTS): Supply costs for 750 multiply/divide operations. + (rs6000_adjust_priority): Add declaration. + + * config/rs6000/rs6000.c (rs6000_override_options): + -mcpu={750,740} now sets the processor type as 750, not 603. + Allow -mmultiple and -mstring on little endian 750 systems. + (rs6000_adjust_priority): Stub for now. + (get_issue_rate): The PowerPC 750 can issue 2 instructions/cycle. + + * config/rs6000/rs6000.md (function/cpu attributes): Add initial + ppc750 support. + + * config/rs6000/sysv4.h (STRICT_ALIGNMENT): Don't force strict + alignment if little endian. + (CC1_SPEC): Pass -mstrict-align if little endian, and not + overridden. + (CC1_ENDIAN_{LITTLE,BIG,DEFAULT}_SPEC): Endian specific configs. + (SUBTARGET_EXTRA_SPECS): Add cc1 endian specs. + + * config/rs6000/{sysv4,eabi}le.h (CC1_ENDIAN_DEFAULT_SPEC): + Override, default is little endian. + + * config/rs6000/t-ppcgas (MULTILIB_*): Delete obsolete Solaris + multilibs. + Sat Jan 9 23:54:09 1999 Kaveh R. Ghazi * gcc.c (xstrerror): Renamed from my_strerror. All callers diff --git a/gcc/config/rs6000/eabile.h b/gcc/config/rs6000/eabile.h index 78dc7bc..97e2b7c 100644 --- a/gcc/config/rs6000/eabile.h +++ b/gcc/config/rs6000/eabile.h @@ -28,6 +28,9 @@ Boston, MA 02111-1307, USA. */ #undef CPP_ENDIAN_DEFAULT_SPEC #define CPP_ENDIAN_DEFAULT_SPEC "%(cpp_endian_little)" +#undef CC1_ENDIAN_DEFAULT_SPEC +#define CC1_ENDIAN_DEFAULT_SPEC "%(cc1_endian_little)" + #undef LINK_TARGET_SPEC #define LINK_TARGET_SPEC "\ %{mbig: -oformat elf32-powerpc } %{mbig-endian: -oformat elf32-powerpc } \ diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index ac5efe5..afb17f9 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -234,6 +234,12 @@ rs6000_override_options (default_cpu) {"620", PROCESSOR_PPC620, MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, POWER_MASKS | MASK_PPC_GPOPT}, + {"740", PROCESSOR_PPC750, + MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, + POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, + {"750", PROCESSOR_PPC750, + MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, + POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, {"801", PROCESSOR_MPCCORE, MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, @@ -297,9 +303,12 @@ rs6000_override_options (default_cpu) if (TARGET_STRING_SET) target_flags = (target_flags & ~MASK_STRING) | string; - /* Don't allow -mmultiple or -mstring on little endian systems, because the - hardware doesn't support the instructions used in little endian mode */ - if (!BYTES_BIG_ENDIAN) + /* Don't allow -mmultiple or -mstring on little endian systems unless the cpu + is a 750, because the hardware doesn't support the instructions used in + little endian mode, and causes an alignment trap. The 750 does not cause + an alignment trap (except when the target is unaligned). */ + + if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750) { if (TARGET_MULTIPLE) { @@ -497,7 +506,8 @@ short_cint_operand (op, mode) enum machine_mode mode ATTRIBUTE_UNUSED; { return ((GET_CODE (op) == CONST_INT - && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) < 0x10000)); + && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) < 0x10000) + || GET_CODE (op) == CONSTANT_P_RTX); } /* Similar for a unsigned D field. */ @@ -508,7 +518,8 @@ u_short_cint_operand (op, mode) enum machine_mode mode ATTRIBUTE_UNUSED; { return ((GET_CODE (op) == CONST_INT - && (INTVAL (op) & (~ (HOST_WIDE_INT) 0xffff)) == 0)); + && (INTVAL (op) & (~ (HOST_WIDE_INT) 0xffff)) == 0) + || GET_CODE (op) == CONSTANT_P_RTX); } /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */ @@ -596,6 +607,7 @@ reg_or_cint_operand (op, mode) enum machine_mode mode; { return (GET_CODE (op) == CONST_INT + || GET_CODE (op) == CONSTANT_P_RTX || gpc_reg_operand (op, mode)); } @@ -880,7 +892,8 @@ logical_operand (op, mode) return (gpc_reg_operand (op, mode) || (GET_CODE (op) == CONST_INT && ((INTVAL (op) & (~ (HOST_WIDE_INT) 0xffff)) == 0 - || (INTVAL (op) & 0xffff) == 0))); + || (INTVAL (op) & 0xffff) == 0)) + || GET_CODE (op) == CONSTANT_P_RTX); } /* Return 1 if C is a constant that is not a logical operand (as @@ -1106,10 +1119,6 @@ input_operand (op, mode) if (memory_operand (op, mode)) return 1; - /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */ - if (GET_CODE (op) == CONST && GET_CODE (XEXP (op, 0)) == CONSTANT_P_RTX) - return 1; - /* For floating-point, easy constants are valid. */ if (GET_MODE_CLASS (mode) == MODE_FLOAT && CONSTANT_P (op) @@ -1119,6 +1128,7 @@ input_operand (op, mode) /* Allow any integer constant. */ if (GET_MODE_CLASS (mode) == MODE_INT && (GET_CODE (op) == CONST_INT + || GET_CODE (op) == CONSTANT_P_RTX || GET_CODE (op) == CONST_DOUBLE)) return 1; @@ -2746,15 +2756,15 @@ print_operand (file, x, code) /* If the high bit is set and the low bit is not, the value is zero. If the high bit is zero, the value is the first 1 bit we find from the left. */ - if ((val & 0x80000000) && ((val & 1) == 0)) + if (val < 0 && (val & 1) == 0) { putc ('0', file); return; } - else if ((val & 0x80000000) == 0) + else if (val >= 0) { for (i = 1; i < 32; i++) - if ((val <<= 1) & 0x80000000) + if ((val <<= 1) < 0) break; fprintf (file, "%d", i); return; @@ -2781,7 +2791,7 @@ print_operand (file, x, code) /* If the low bit is set and the high bit is not, the value is 31. If the low bit is zero, the value is the first 1 bit we find from the right. */ - if ((val & 1) && ((val & 0x80000000) == 0)) + if ((val & 1) && val >= 0) { fputs ("31", file); return; @@ -2801,7 +2811,7 @@ print_operand (file, x, code) /* Otherwise, look for the first 0 bit from the left. The result is its number minus 1. We know the high-order bit is one. */ for (i = 0; i < 32; i++) - if (((val <<= 1) & 0x80000000) == 0) + if ((val <<= 1) >= 0) break; fprintf (file, "%d", i); @@ -3447,6 +3457,7 @@ rs6000_stack_info () } } + /* Determine if we need to save the link register */ if (regs_ever_live[65] || (DEFAULT_ABI == ABI_AIX && profile_flag) @@ -3473,6 +3484,13 @@ rs6000_stack_info () info_ptr->cr_size = reg_size; } + /* Ensure that fp_save_offset will be aligned to an 8-byte boundary. */ + if (info_ptr->fpmem_p) + { + info_ptr->gp_size = RS6000_ALIGN (info_ptr->gp_size, 8); + info_ptr->main_size = RS6000_ALIGN (info_ptr->main_size, 8); + } + /* Determine various sizes */ info_ptr->reg_size = reg_size; info_ptr->fixed_size = RS6000_SAVE_AREA; @@ -3526,7 +3544,6 @@ rs6000_stack_info () break; } - /* Ensure that fpmem_offset will be aligned to an 8-byte boundary. */ if (info_ptr->fpmem_p && (info_ptr->main_save_offset - info_ptr->fpmem_size) % 8) info_ptr->fpmem_size += reg_size; @@ -5118,6 +5135,48 @@ rs6000_adjust_cost (insn, link, dep_insn, cost) return cost; } +/* A C statement (sans semicolon) to update the integer scheduling priority + INSN_PRIORITY (INSN). Reduce the priority to execute the INSN earlier, + increase the priority to execute INSN later. Do not define this macro if + you do not need to adjust the scheduling priorities of insns. */ + +int +rs6000_adjust_priority (insn, priority) + rtx insn; + int priority; +{ + /* On machines (like the 750) which have asymetric integer units, where one + integer unit can do multiply and divides and the other can't, reduce the + priority of multiply/divide so it is scheduled before other integer + operationss. */ + +#if 0 + if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') + return priority; + + if (GET_CODE (PATTERN (insn)) == USE) + return priority; + + switch (rs6000_cpu_attr) { + case CPU_PPC750: + switch (get_attr_type (insn)) + { + default: + break; + + case TYPE_IMUL: + case TYPE_IDIV: + fprintf (stderr, "priority was %#x (%d) before adjustment\n", priority, priority); + if (priority >= 0 && priority < 0x01000000) + priority >>= 3; + break; + } + } +#endif + + return priority; +} + /* Return how many instructions the machine can issue per cycle */ int get_issue_rate() { @@ -5130,6 +5189,8 @@ int get_issue_rate() return 3; /* ? */ case CPU_PPC603: return 2; + case CPU_PPC750: + return 2; case CPU_PPC604: return 4; case CPU_PPC620: diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 889ef98..3872fdd 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for IBM RS/6000. - Copyright (C) 1992, 93-8, 1999 Free Software Foundation, Inc. + Copyright (C) 1992, 93-7, 1998 Free Software Foundation, Inc. Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) This file is part of GNU CC. @@ -81,6 +81,9 @@ Boston, MA 02111-1307, USA. */ %{mcpu=604: -D_ARCH_PPC} \ %{mcpu=604e: -D_ARCH_PPC} \ %{mcpu=620: -D_ARCH_PPC} \ +%{mcpu=740: -D_ARCH_PPC} \ +%{mcpu=750: -D_ARCH_PPC} \ +%{mcpu=801: -D_ARCH_PPC} \ %{mcpu=821: -D_ARCH_PPC} \ %{mcpu=823: -D_ARCH_PPC} \ %{mcpu=860: -D_ARCH_PPC}" @@ -134,6 +137,8 @@ Boston, MA 02111-1307, USA. */ %{mcpu=604: -mppc} \ %{mcpu=604e: -mppc} \ %{mcpu=620: -mppc} \ +%{mcpu=740: -mppc} \ +%{mcpu=750: -mppc} \ %{mcpu=821: -mppc} \ %{mcpu=823: -mppc} \ %{mcpu=860: -mppc}" @@ -391,15 +396,18 @@ extern int target_flags; /* Processor type. Order must match cpu attribute in MD file. */ enum processor_type - {PROCESSOR_RIOS1, - PROCESSOR_RIOS2, - PROCESSOR_MPCCORE, - PROCESSOR_PPC403, - PROCESSOR_PPC601, - PROCESSOR_PPC603, - PROCESSOR_PPC604, - PROCESSOR_PPC604e, - PROCESSOR_PPC620}; + { + PROCESSOR_RIOS1, + PROCESSOR_RIOS2, + PROCESSOR_MPCCORE, + PROCESSOR_PPC403, + PROCESSOR_PPC601, + PROCESSOR_PPC603, + PROCESSOR_PPC604, + PROCESSOR_PPC604e, + PROCESSOR_PPC620, + PROCESSOR_PPC750 + }; extern enum processor_type rs6000_cpu; @@ -855,6 +863,14 @@ extern int rs6000_debug_arg; /* debug argument handling */ #define ADJUST_COST(INSN,LINK,DEP_INSN,COST) \ (COST) = rs6000_adjust_cost (INSN,LINK,DEP_INSN,COST) +/* A C statement (sans semicolon) to update the integer scheduling priority + INSN_PRIORITY (INSN). Reduce the priority to execute the INSN earlier, + increase the priority to execute INSN later. Do not define this macro if + you do not need to adjust the scheduling priorities of insns. */ + +#define ADJUST_PRIORITY(INSN) \ + INSN_PRIORITY (INSN) = rs6000_adjust_priority (INSN, INSN_PRIORITY (INSN)) + /* Define this macro to change register usage conditional on target flags. Set MQ register fixed (already call_used) if not POWER architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not be allocated. @@ -2280,6 +2296,7 @@ do { \ case PROCESSOR_PPC601: \ return COSTS_N_INSNS (5); \ case PROCESSOR_PPC603: \ + case PROCESSOR_PPC750: \ return (GET_CODE (XEXP (X, 1)) != CONST_INT \ ? COSTS_N_INSNS (5) \ : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \ @@ -2315,6 +2332,8 @@ do { \ case PROCESSOR_PPC604e: \ case PROCESSOR_PPC620: \ return COSTS_N_INSNS (20); \ + case PROCESSOR_PPC750: \ + return COSTS_N_INSNS (19); \ } \ case FFS: \ return COSTS_N_INSNS (4); \ @@ -3169,15 +3188,15 @@ do { \ /* Define the codes that are matched by predicates in rs6000.c. */ #define PREDICATE_CODES \ - {"short_cint_operand", {CONST_INT}}, \ - {"u_short_cint_operand", {CONST_INT}}, \ + {"short_cint_operand", {CONST_INT, CONSTANT_P_RTX}}, \ + {"u_short_cint_operand", {CONST_INT, CONSTANT_P_RTX}}, \ {"non_short_cint_operand", {CONST_INT}}, \ {"gpc_reg_operand", {SUBREG, REG}}, \ {"cc_reg_operand", {SUBREG, REG}}, \ - {"reg_or_short_operand", {SUBREG, REG, CONST_INT}}, \ + {"reg_or_short_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \ {"reg_or_neg_short_operand", {SUBREG, REG, CONST_INT}}, \ - {"reg_or_u_short_operand", {SUBREG, REG, CONST_INT}}, \ - {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \ + {"reg_or_u_short_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \ + {"reg_or_cint_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \ {"got_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \ {"got_no_const_operand", {SYMBOL_REF, LABEL_REF}}, \ {"easy_fp_constant", {CONST_DOUBLE}}, \ @@ -3186,11 +3205,12 @@ do { \ {"volatile_mem_operand", {MEM}}, \ {"offsettable_addr_operand", {REG, SUBREG, PLUS}}, \ {"mem_or_easy_const_operand", {SUBREG, MEM, CONST_DOUBLE}}, \ - {"add_operand", {SUBREG, REG, CONST_INT}}, \ + {"add_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \ {"non_add_cint_operand", {CONST_INT}}, \ - {"and_operand", {SUBREG, REG, CONST_INT}}, \ - {"and64_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ - {"logical_operand", {SUBREG, REG, CONST_INT}}, \ + {"and_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \ + {"and64_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX, \ + CONST_DOUBLE}}, \ + {"logical_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \ {"non_logical_cint_operand", {CONST_INT}}, \ {"mask_operand", {CONST_INT}}, \ {"mask64_operand", {CONST_INT, CONST_DOUBLE}}, \ @@ -3198,7 +3218,7 @@ do { \ {"fpmem_operand", {REG}}, \ {"call_operand", {SYMBOL_REF, REG}}, \ {"current_file_function_operand", {SYMBOL_REF}}, \ - {"input_operand", {SUBREG, MEM, REG, CONST_INT, \ + {"input_operand", {SUBREG, MEM, REG, CONST_INT, CONSTANT_P_RTX, \ CONST_DOUBLE, SYMBOL_REF}}, \ {"load_multiple_operation", {PARALLEL}}, \ {"store_multiple_operation", {PARALLEL}}, \ @@ -3306,6 +3326,7 @@ extern void output_ascii (); extern void rs6000_gen_section_name (); extern void output_function_profiler (); extern int rs6000_adjust_cost (); +extern int rs6000_adjust_priority (); extern void rs6000_trampoline_template (); extern int rs6000_trampoline_size (); extern void rs6000_initialize_trampoline (); diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index ac7008f..6fb8372 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -1,5 +1,5 @@ ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler -;; Copyright (C) 1990, 91-98, 1999 Free Software Foundation, Inc. +;; Copyright (C) 1990, 91-97, 1998 Free Software Foundation, Inc. ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) ;; This file is part of GNU CC. @@ -40,7 +40,7 @@ ;; Processor type -- this attribute must exactly match the processor_type ;; enumeration in rs6000.h. -(define_attr "cpu" "rios1,rios2,mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620" +(define_attr "cpu" "rios1,rios2,mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc750" (const (symbol_ref "rs6000_cpu_attr"))) ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY @@ -50,17 +50,17 @@ ; (POWER and 601 use Integer Unit) (define_function_unit "lsu" 1 0 (and (eq_attr "type" "load") - (eq_attr "cpu" "mpccore,ppc603,ppc604,ppc604e,ppc620")) + (eq_attr "cpu" "mpccore,ppc603,ppc604,ppc604e,ppc620,ppc750")) 2 1) (define_function_unit "lsu" 1 0 (and (eq_attr "type" "store,fpstore") - (eq_attr "cpu" "mpccore,ppc603,ppc604,ppc604e,ppc620")) + (eq_attr "cpu" "mpccore,ppc603,ppc604,ppc604e,ppc620,ppc750")) 1 1) (define_function_unit "lsu" 1 0 (and (eq_attr "type" "fpload") - (eq_attr "cpu" "mpccore,ppc603")) + (eq_attr "cpu" "mpccore,ppc603,ppc750")) 2 1) (define_function_unit "lsu" 1 0 @@ -68,6 +68,31 @@ (eq_attr "cpu" "ppc604,ppc604e,ppc620")) 3 1) +; PPC750 has two integer units: a primary one which can perform all +; operations and a secondary one which is fed in lock step with the first +; and can perform "simple" integer operations. +; To catch this we define a 'dummy' imuldiv-unit that is also needed +; for the complex insns. +(define_function_unit "iu2" 2 0 + (and (eq_attr "type" "integer") + (eq_attr "cpu" "ppc750")) + 1 1) + +(define_function_unit "iu2" 2 0 + (and (eq_attr "type" "imul") + (eq_attr "cpu" "ppc750")) + 4 2) + +(define_function_unit "imuldiv" 1 0 + (and (eq_attr "type" "imul") + (eq_attr "cpu" "ppc750")) + 4 2) + +(define_function_unit "imuldiv" 1 0 + (and (eq_attr "type" "idiv") + (eq_attr "cpu" "ppc750")) + 19 19) + (define_function_unit "iu" 1 0 (and (eq_attr "type" "load") (eq_attr "cpu" "rios1,ppc403,ppc601")) @@ -218,7 +243,7 @@ (define_function_unit "iu" 1 0 (and (eq_attr "type" "compare,delayed_compare") - (eq_attr "cpu" "mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620")) + (eq_attr "cpu" "mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc750")) 3 1) (define_function_unit "iu2" 2 0 @@ -228,7 +253,7 @@ (define_function_unit "iu2" 2 0 (and (eq_attr "type" "compare,delayed_compare") - (eq_attr "cpu" "ppc604,ppc604e,ppc620")) + (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc750")) 1 1) ; fp compare uses fp unit @@ -255,7 +280,7 @@ ; fp compare uses fp unit (define_function_unit "fpu" 1 0 (and (eq_attr "type" "fpcompare") - (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc604e,ppc620")) + (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc604e,ppc620,ppc750")) 5 1) (define_function_unit "fpu" 1 0 @@ -270,7 +295,7 @@ (define_function_unit "bpu" 1 0 (and (eq_attr "type" "mtjmpr") - (eq_attr "cpu" "mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620")) + (eq_attr "cpu" "mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc750")) 4 1) ; all jumps/branches are executing on the bpu, in 1 cycle, for all machines. @@ -300,7 +325,7 @@ (define_function_unit "fpu" 1 0 (and (eq_attr "type" "fp") - (eq_attr "cpu" "ppc603,ppc604,ppc604e,ppc620")) + (eq_attr "cpu" "ppc603,ppc604,ppc604e,ppc620,ppc750")) 3 1) (define_function_unit "fpu" 1 0 @@ -316,7 +341,7 @@ ; is this true? (define_function_unit "fpu" 1 0 (and (eq_attr "type" "dmul") - (eq_attr "cpu" "ppc603")) + (eq_attr "cpu" "ppc603,ppc750")) 4 2) (define_function_unit "fpu" 1 0 @@ -351,7 +376,7 @@ (define_function_unit "fpu" 1 0 (and (eq_attr "type" "ddiv") - (eq_attr "cpu" "ppc601,ppc604,ppc604e,ppc620")) + (eq_attr "cpu" "ppc601,ppc604,ppc604e,ppc620,ppc750")) 31 31) (define_function_unit "fpu" 1 0 @@ -5399,14 +5424,6 @@ if (GET_CODE (operands[1]) == CONST_DOUBLE) operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); - /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */ - if (GET_CODE (operands[1]) == CONST - && GET_CODE (XEXP (operands[1], 0)) == CONSTANT_P_RTX) - { - emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); - DONE; - } - /* Use default pattern for address of ELF small data */ if (TARGET_ELF && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) @@ -5428,7 +5445,8 @@ && !flag_pic && CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != HIGH - && GET_CODE (operands[1]) != CONST_INT) + && GET_CODE (operands[1]) != CONST_INT + && GET_CODE (operands[1]) != CONSTANT_P_RTX) { rtx target = (reload_completed || reload_in_progress) ? operands[0] : gen_reg_rtx (SImode); @@ -5482,6 +5500,7 @@ if ((!TARGET_WINDOWS_NT || DEFAULT_ABI != ABI_NT) && CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT + && GET_CODE (operands[1]) != CONSTANT_P_RTX && GET_CODE (operands[1]) != HIGH && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1])) { @@ -5580,7 +5599,8 @@ operands[1] = force_reg (HImode, operands[1]); if (CONSTANT_P (operands[1]) - && GET_CODE (operands[1]) != CONST_INT) + && GET_CODE (operands[1]) != CONST_INT + && GET_CODE (operands[1]) != CONSTANT_P_RTX) { operands[1] = force_const_mem (HImode, operands[1]); if (! memory_address_p (HImode, XEXP (operands[1], 0)) @@ -5616,7 +5636,8 @@ operands[1] = force_reg (QImode, operands[1]); if (CONSTANT_P (operands[1]) - && GET_CODE (operands[1]) != CONST_INT) + && GET_CODE (operands[1]) != CONST_INT + && GET_CODE (operands[1]) != CONSTANT_P_RTX) { operands[1] = force_const_mem (QImode, operands[1]); if (! memory_address_p (QImode, XEXP (operands[1], 0)) @@ -6016,18 +6037,11 @@ ) operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); - /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */ - if (GET_CODE (operands[1]) == CONST - && GET_CODE (XEXP (operands[1], 0)) == CONSTANT_P_RTX) - { - emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); - DONE; - } - if (TARGET_64BIT && CONSTANT_P (operands[1]) #if HOST_BITS_PER_WIDE_INT == 32 && GET_CODE (operands[1]) != CONST_INT + && GET_CODE (operands[1]) != CONSTANT_P_RTX #endif && ! easy_fp_constant (operands[1], DImode) && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1])) diff --git a/gcc/config/rs6000/sysv4.h b/gcc/config/rs6000/sysv4.h index 7184555..7262c3d 100644 --- a/gcc/config/rs6000/sysv4.h +++ b/gcc/config/rs6000/sysv4.h @@ -393,12 +393,9 @@ do { \ /* Define this macro to be the value 1 if instructions will fail to work if given data not on the nominal alignment. If instructions - will merely go slower in that case, define this macro as 0. - - Note, little endian systems trap on unaligned addresses, so never - turn off strict alignment in that case. */ + will merely go slower in that case, define this macro as 0. */ #undef STRICT_ALIGNMENT -#define STRICT_ALIGNMENT (TARGET_STRICT_ALIGN || TARGET_LITTLE_ENDIAN) +#define STRICT_ALIGNMENT (TARGET_STRICT_ALIGN) /* Alignment in bits of the stack boundary. Note, in order to allow building one set of libraries with -mno-eabi instead of eabi libraries and non-eabi @@ -975,16 +972,38 @@ do { \ %{memb} %{!memb: %{msdata: -memb} %{msdata=eabi: -memb}} \ %{mlittle} %{mlittle-endian} %{mbig} %{mbig-endian} \ %{!mlittle: %{!mlittle-endian: %{!mbig: %{!mbig-endian: \ - %{mcall-solaris: -mlittle -msolaris} %{mcall-linux: -mbig} }}}}" + %{mcall-solaris: -mlittle -msolaris} \ + %{mcall-linux: -mbig} }}}}" + +#ifndef CC1_ENDIAN_BIG_SPEC +#define CC1_ENDIAN_BIG_SPEC "" +#endif + +#ifndef CC1_ENDIAN_LITTLE_SPEC +#define CC1_ENDIAN_LITTLE_SPEC "\ +%{!mstrict-align: %{!mno-strict-align: \ + -mstrict-align \ +}}" +#endif + +#ifndef CC1_ENDIAN_DEFAULT_SPEC +#define CC1_ENDIAN_DEFAULT_SPEC "%(cc1_endian_big_spec)" +#endif #undef CC1_SPEC /* Pass -G xxx to the compiler and set correct endian mode */ #define CC1_SPEC "%{G*} \ +%{mlittle: %(cc1_endian_little)} %{!mlittle: %{mlittle-endian: %(cc1_endian_little)}} \ +%{mbig: %(cc1_endian_big)} %{!mbig: %{mbig-endian: %(cc1_endian_big)}} \ %{!mlittle: %{!mlittle-endian: %{!mbig: %{!mbig-endian: \ - %{mcall-nt: -mlittle } \ - %{mcall-aixdesc: -mbig } \ - %{mcall-solaris: -mlittle } \ - %{mcall-linux: -mbig} }}}} \ + %{mcall-nt: -mlittle %{cc1_endian_little} } \ + %{mcall-aixdesc: -mbig %{cc1_endian_big} } \ + %{mcall-solaris: -mlittle %{cc1_endian_little} } \ + %{mcall-linux: -mbig %{cc1_endian_big}}} \ + %{!mcall-nt: %{!mcall-aixdesc: %{!mcall-solaris: %{!mcall-linux: \ + %(cc1_endian_default) \ + }}}} \ +}}} \ %{mcall-solaris: -mregnames } \ %{mno-sdata: -msdata=none } \ %{meabi: %{!mcall-*: -mcall-sysv }} \ @@ -1068,7 +1087,8 @@ do { \ #undef LINK_TARGET_SPEC #define LINK_TARGET_SPEC "\ %{mlittle: -oformat elf32-powerpcle } %{mlittle-endian: -oformat elf32-powerpcle } \ -%{!mlittle: %{!mlittle-endian: %{!mbig: %{!mbig-endian: %{mcall-solaris: -oformat elf32-powerpcle}}}}}" +%{!mlittle: %{!mlittle-endian: %{!mbig: %{!mbig-endian: \ + %{mcall-solaris: -oformat elf32-powerpcle}}}}}" /* Any specific OS flags */ #ifndef LINK_OS_SPEC @@ -1419,6 +1439,9 @@ do { \ { "link_os_linux", LINK_OS_LINUX_SPEC }, \ { "link_os_solaris", LINK_OS_SOLARIS_SPEC }, \ { "link_os_default", LINK_OS_DEFAULT_SPEC }, \ + { "cc1_endian_big", CC1_ENDIAN_BIG_SPEC }, \ + { "cc1_endian_little", CC1_ENDIAN_LITTLE_SPEC }, \ + { "cc1_endian_default", CC1_ENDIAN_DEFAULT_SPEC }, \ { "cpp_endian_big", CPP_ENDIAN_BIG_SPEC }, \ { "cpp_endian_little", CPP_ENDIAN_LITTLE_SPEC }, \ { "cpp_endian_solaris", CPP_ENDIAN_SOLARIS_SPEC }, \ diff --git a/gcc/config/rs6000/sysv4le.h b/gcc/config/rs6000/sysv4le.h index 0cf2ec4..1e21acd 100644 --- a/gcc/config/rs6000/sysv4le.h +++ b/gcc/config/rs6000/sysv4le.h @@ -28,6 +28,9 @@ Boston, MA 02111-1307, USA. */ #undef CPP_ENDIAN_DEFAULT_SPEC #define CPP_ENDIAN_DEFAULT_SPEC "%(cpp_endian_little)" +#undef CC1_ENDIAN_DEFAULT_SPEC +#define CC1_ENDIAN_DEFAULT_SPEC "%(cc1_endian_little)" + #undef LINK_TARGET_SPEC #define LINK_TARGET_SPEC "\ %{mbig: -oformat elf32-powerpc } %{mbig-endian: -oformat elf32-powerpc } \ diff --git a/gcc/config/rs6000/t-ppcgas b/gcc/config/rs6000/t-ppcgas index 9fb5e4e..8ea37be 100644 --- a/gcc/config/rs6000/t-ppcgas +++ b/gcc/config/rs6000/t-ppcgas @@ -3,17 +3,14 @@ MULTILIB_OPTIONS = msoft-float \ mlittle/mbig \ - mcall-sysv/mcall-aix/mcall-solaris/mcall-linux + mcall-sysv/mcall-aix/mcall-linux MULTILIB_DIRNAMES = nof \ le be \ - cs ca sol lin + cs ca lin MULTILIB_EXTRA_OPTS = mrelocatable-lib mno-eabi mstrict-align -MULTILIB_EXCEPTIONS = *mbig/*mcall-solaris* \ - *mlittle/*mcall-solaris* \ - *msoft-float/*mcall-solaris* \ - *mbig/*mcall-linux* \ +MULTILIB_EXCEPTIONS = *mbig/*mcall-linux* \ *mlittle/*mcall-linux* \ *msoft-float/*mcall-linux* diff --git a/gcc/invoke.texi b/gcc/invoke.texi index 52291d3..f930e9d 100644 --- a/gcc/invoke.texi +++ b/gcc/invoke.texi @@ -4285,13 +4285,13 @@ Set architecture type, register usage, choice of mnemonics, and instruction scheduling parameters for machine type @var{cpu_type}. Supported values for @var{cpu_type} are @samp{rs6000}, @samp{rios1}, @samp{rios2}, @samp{rsc}, @samp{601}, @samp{602}, @samp{603}, -@samp{603e}, @samp{604}, @samp{604e}, @samp{620}, @samp{power}, -@samp{power2}, @samp{powerpc}, @samp{403}, @samp{505}, @samp{801}, -@samp{821}, @samp{823}, and @samp{860} and @samp{common}. -@samp{-mcpu=power}, @samp{-mcpu=power2}, and @samp{-mcpu=powerpc} -specify generic POWER, POWER2 and pure PowerPC (i.e., not MPC601) -architecture machine types, with an appropriate, generic processor model -assumed for scheduling purposes.@refill +@samp{603e}, @samp{604}, @samp{604e}, @samp{620}, @samp{740}, +@samp{750}, @samp{power}, @samp{power2}, @samp{powerpc}, @samp{403}, +@samp{505}, @samp{801}, @samp{821}, @samp{823}, and @samp{860} and +@samp{common}. @samp{-mcpu=power}, @samp{-mcpu=power2}, and +@samp{-mcpu=powerpc} specify generic POWER, POWER2 and pure PowerPC +(i.e., not MPC601) architecture machine types, with an appropriate, +generic processor model assumed for scheduling purposes.@refill @c overfull hbox here --bob 22 jul96 @c original text between ignore ... end ignore @@ -4435,17 +4435,20 @@ instructions and the store multiple word instructions. These instructions are generated by default on POWER systems, and not generated on PowerPC systems. Do not use @samp{-mmultiple} on little endian PowerPC systems, since those instructions do not work when the -processor is in little endian mode. +processor is in little endian mode. The exceptions are PPC740 and +PPC750 which permit the instructions usage in little endian mode. @item -mstring @itemx -mno-string @kindex -mstring -Generate code that uses (does not use) the load string instructions and the -store string word instructions to save multiple registers and do small block -moves. These instructions are generated by default on POWER systems, and not -generated on PowerPC systems. Do not use @samp{-mstring} on little endian -PowerPC systems, since those instructions do not work when the processor is in -little endian mode. +Generate code that uses (does not use) the load string instructions +and the store string word instructions to save multiple registers and +do small block moves. These instructions are generated by default on +POWER systems, and not generated on PowerPC systems. Do not use +@samp{-mstring} on little endian PowerPC systems, since those +instructions do not work when the processor is in little endian mode. +The exceptions are PPC740 and PPC750 which permit the instructions +usage in little endian mode. @item -mupdate @itemx -mno-update -- 2.7.4