From 946fe976fded7fb2784e3662e905d63743cf4aec Mon Sep 17 00:00:00 2001 From: Evandro Menezes Date: Fri, 11 Jan 2019 19:36:27 +0000 Subject: [PATCH] [llvm-mca] Update tests for Exynos (NFC) Update test cases for Exynos M4. llvm-svn: 350961 --- llvm/test/tools/llvm-mca/AArch64/Exynos/direct-branch.s | 8 ++++++++ .../tools/llvm-mca/AArch64/Exynos/extended-register.s | 16 ++++++++++++++++ .../llvm-mca/AArch64/Exynos/scheduler-queue-usage.s | 6 ++++++ .../tools/llvm-mca/AArch64/Exynos/shifted-register.s | 16 ++++++++++++++++ 4 files changed, 46 insertions(+) diff --git a/llvm/test/tools/llvm-mca/AArch64/Exynos/direct-branch.s b/llvm/test/tools/llvm-mca/AArch64/Exynos/direct-branch.s index 7c3cc8f..cd31d0b 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Exynos/direct-branch.s +++ b/llvm/test/tools/llvm-mca/AArch64/Exynos/direct-branch.s @@ -1,6 +1,7 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m1 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M1 # RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m3 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M3 +# RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m4 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M4 b main @@ -9,6 +10,7 @@ # M1-NEXT: Total Cycles: 26 # M3-NEXT: Total Cycles: 18 +# M4-NEXT: Total Cycles: 18 # ALL-NEXT: Total uOps: 100 @@ -22,6 +24,11 @@ # M3-NEXT: IPC: 5.56 # M3-NEXT: Block RThroughput: 0.2 +# M4: Dispatch Width: 6 +# M4-NEXT: uOps Per Cycle: 5.56 +# M4-NEXT: IPC: 5.56 +# M4-NEXT: Block RThroughput: 0.2 + # ALL: Instruction Info: # ALL-NEXT: [1]: #uOps # ALL-NEXT: [2]: Latency @@ -34,3 +41,4 @@ # M1-NEXT: 1 0 0.25 b main # M3-NEXT: 1 0 0.17 b main +# M4-NEXT: 1 0 0.17 b main diff --git a/llvm/test/tools/llvm-mca/AArch64/Exynos/extended-register.s b/llvm/test/tools/llvm-mca/AArch64/Exynos/extended-register.s index f136bd3..7044f64 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Exynos/extended-register.s +++ b/llvm/test/tools/llvm-mca/AArch64/Exynos/extended-register.s @@ -1,6 +1,7 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # RUN: llvm-mca -march=aarch64 -mcpu=exynos-m1 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,EM1 # RUN: llvm-mca -march=aarch64 -mcpu=exynos-m3 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,EM3 +# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m4 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,EM4 sub w0, w1, w2, sxtb #0 add x3, x4, w5, sxth #1 @@ -16,6 +17,7 @@ # EM1-NEXT: Total Cycles: 403 # EM3-NEXT: Total Cycles: 304 +# EM4-NEXT: Total Cycles: 304 # ALL-NEXT: Total uOps: 800 @@ -29,6 +31,11 @@ # EM3-NEXT: IPC: 2.63 # EM3-NEXT: Block RThroughput: 3.0 +# EM4: Dispatch Width: 6 +# EM4-NEXT: uOps Per Cycle: 2.63 +# EM4-NEXT: IPC: 2.63 +# EM4-NEXT: Block RThroughput: 3.0 + # ALL: Instruction Info: # ALL-NEXT: [1]: #uOps # ALL-NEXT: [2]: Latency @@ -56,3 +63,12 @@ # EM3-NEXT: 1 2 0.50 add x15, x16, w17, uxth #1 # EM3-NEXT: 1 2 0.50 subs x18, x19, w20, sxtw #2 # EM3-NEXT: 1 2 0.50 adds x21, x22, x23, sxtx #3 + +# EM4-NEXT: 1 1 0.25 sub w0, w1, w2, sxtb +# EM4-NEXT: 1 2 0.50 add x3, x4, w5, sxth #1 +# EM4-NEXT: 1 1 0.25 subs x6, x7, w8, uxtw #2 +# EM4-NEXT: 1 1 0.25 adds x9, x10, x11, uxtx #3 +# EM4-NEXT: 1 1 0.25 sub w12, w13, w14, uxtb +# EM4-NEXT: 1 2 0.50 add x15, x16, w17, uxth #1 +# EM4-NEXT: 1 2 0.50 subs x18, x19, w20, sxtw #2 +# EM4-NEXT: 1 2 0.50 adds x21, x22, x23, sxtx #3 diff --git a/llvm/test/tools/llvm-mca/AArch64/Exynos/scheduler-queue-usage.s b/llvm/test/tools/llvm-mca/AArch64/Exynos/scheduler-queue-usage.s index bccae7d..8a2c780 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Exynos/scheduler-queue-usage.s +++ b/llvm/test/tools/llvm-mca/AArch64/Exynos/scheduler-queue-usage.s @@ -1,6 +1,7 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # RUN: llvm-mca -march=aarch64 -mcpu=exynos-m1 -iterations=1 -scheduler-stats -resource-pressure=false -instruction-info=false < %s | FileCheck %s -check-prefixes=ALL,M1 # RUN: llvm-mca -march=aarch64 -mcpu=exynos-m3 -iterations=1 -scheduler-stats -resource-pressure=false -instruction-info=false < %s | FileCheck %s -check-prefixes=ALL,M3 +# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m4 -iterations=1 -scheduler-stats -resource-pressure=false -instruction-info=false < %s | FileCheck %s -check-prefixes=ALL,M4 b main @@ -19,6 +20,11 @@ # M3-NEXT: IPC: 0.50 # M3-NEXT: Block RThroughput: 0.2 +# M4: Dispatch Width: 6 +# M4-NEXT: uOps Per Cycle: 0.50 +# M4-NEXT: IPC: 0.50 +# M4-NEXT: Block RThroughput: 0.2 + # ALL: Schedulers - number of cycles where we saw N instructions issued: # ALL-NEXT: [# issued], [# cycles] # ALL-NEXT: 0, 1 (50.0%) diff --git a/llvm/test/tools/llvm-mca/AArch64/Exynos/shifted-register.s b/llvm/test/tools/llvm-mca/AArch64/Exynos/shifted-register.s index fd6f4dd..5dfdc1e 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Exynos/shifted-register.s +++ b/llvm/test/tools/llvm-mca/AArch64/Exynos/shifted-register.s @@ -1,6 +1,7 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # RUN: llvm-mca -march=aarch64 -mcpu=exynos-m1 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,EM1 # RUN: llvm-mca -march=aarch64 -mcpu=exynos-m3 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,EM3 +# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m4 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,EM4 adds w0, w1, w2, lsl #0 sub x3, x4, x5, lsr #1 @@ -16,6 +17,7 @@ # EM1-NEXT: Total Cycles: 470 # EM3-NEXT: Total Cycles: 354 +# EM4-NEXT: Total Cycles: 329 # ALL-NEXT: Total uOps: 800 @@ -29,6 +31,11 @@ # EM3-NEXT: IPC: 2.26 # EM3-NEXT: Block RThroughput: 3.5 +# EM4: Dispatch Width: 6 +# EM4-NEXT: uOps Per Cycle: 2.43 +# EM4-NEXT: IPC: 2.43 +# EM4-NEXT: Block RThroughput: 3.3 + # ALL: Instruction Info: # ALL-NEXT: [1]: #uOps # ALL-NEXT: [2]: Latency @@ -56,3 +63,12 @@ # EM3-NEXT: 1 2 0.50 sub x15, x16, x17, lsr #6 # EM3-NEXT: 1 2 0.50 ands x18, x19, x20, lsl #8 # EM3-NEXT: 1 2 0.50 orr w21, w22, w23, asr #10 + +# EM4-NEXT: 1 1 0.25 adds w0, w1, w2 +# EM4-NEXT: 1 2 0.50 sub x3, x4, x5, lsr #1 +# EM4-NEXT: 1 1 0.25 ands x6, x7, x8, lsl #2 +# EM4-NEXT: 1 2 0.50 orr w9, w10, w11, asr #3 +# EM4-NEXT: 1 2 0.50 adds w12, w13, w14, lsl #4 +# EM4-NEXT: 1 2 0.50 sub x15, x16, x17, lsr #6 +# EM4-NEXT: 1 1 0.25 ands x18, x19, x20, lsl #8 +# EM4-NEXT: 1 2 0.50 orr w21, w22, w23, asr #10 -- 2.7.4