From 945fa3bc9dfd0f09fa8cf13602b231ae0a898fff Mon Sep 17 00:00:00 2001 From: Lucas De Marchi Date: Fri, 8 Mar 2019 15:23:21 -0800 Subject: [PATCH] drm/i915: remove ICP_PP_CONTROL MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit This register was placed in the middle of the PP_STATUS definition instead of together with the PP_CONTROL where it should. Since it's not used and there are no current plans to use it, just remove the definition. v2: remove the define rather than moving it. Signed-off-by: Lucas De Marchi Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20190308232321.30168-1-lucas.demarchi@intel.com --- drivers/gpu/drm/i915/i915_reg.h | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index f45b5e8..b273814 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4860,16 +4860,6 @@ enum { #define _PP_STATUS 0x61200 #define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS) #define PP_ON REG_BIT(31) - -#define _PP_CONTROL_1 0xc7204 -#define _PP_CONTROL_2 0xc7304 -#define ICP_PP_CONTROL(x) _MMIO(((x) == 1) ? _PP_CONTROL_1 : \ - _PP_CONTROL_2) -#define POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4) -#define VDD_OVERRIDE_FORCE REG_BIT(3) -#define BACKLIGHT_ENABLE REG_BIT(2) -#define PWR_DOWN_ON_RESET REG_BIT(1) -#define PWR_STATE_TARGET REG_BIT(0) /* * Indicates that all dependencies of the panel are on: * -- 2.7.4