From 94206f1f90fee1b92c49234a17cf8e1781179146 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sun, 31 Jan 2021 19:41:31 -0800 Subject: [PATCH] [PowerPC] Remove vnot_ppc and replace with the standard vnot. immAllOnesV has special support for looking through bitcasts automatically so isel patterns don't need to explicitly look for the bitconvert. --- llvm/lib/Target/PowerPC/PPCInstrAltivec.td | 38 +++++++++++++----------------- llvm/lib/Target/PowerPC/PPCInstrPrefix.td | 21 +++++++---------- llvm/lib/Target/PowerPC/PPCInstrVSX.td | 17 +++++++------ 3 files changed, 33 insertions(+), 43 deletions(-) diff --git a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td index 1a34aa09..6f2313f 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td +++ b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td @@ -30,11 +30,6 @@ // Altivec transformation functions and pattern fragments. // -// Since we canonicalize buildvectors to v16i8, all vnots "-1" operands will be -// of that type. -def vnot_ppc : PatFrag<(ops node:$in), - (xor node:$in, (bitconvert (v16i8 immAllOnesV)))>; - def vpkuhum_shuffle : PatFrag<(ops node:$lhs, node:$rhs), (vector_shuffle node:$lhs, node:$rhs), [{ return PPC::isVPKUHUMShuffleMask(cast(N), 0, *CurDAG); @@ -521,7 +516,7 @@ def VAND : VXForm_1<1028, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VANDC : VXForm_1<1092, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), "vandc $vD, $vA, $vB", IIC_VecFP, [(set v4i32:$vD, (and v4i32:$vA, - (vnot_ppc v4i32:$vB)))]>; + (vnot v4i32:$vB)))]>; def VCFSX : VXForm_1<842, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), "vcfsx $vD, $vB, $UIMM", IIC_VecFP, @@ -684,8 +679,8 @@ let hasSideEffects = 1 in { def VNOR : VXForm_1<1284, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), "vnor $vD, $vA, $vB", IIC_VecFP, - [(set v4i32:$vD, (vnot_ppc (or v4i32:$vA, - v4i32:$vB)))]>; + [(set v4i32:$vD, (vnot (or v4i32:$vA, + v4i32:$vB)))]>; let isCommutable = 1 in { def VOR : VXForm_1<1156, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), "vor $vD, $vA, $vB", IIC_VecFP, @@ -1034,11 +1029,11 @@ def:Pat<(vmrghw_swapped_shuffle v16i8:$vA, v16i8:$vB), (VMRGHW $vB, $vA)>; // Logical Operations -def : Pat<(vnot_ppc v4i32:$vA), (VNOR $vA, $vA)>; +def : Pat<(vnot v4i32:$vA), (VNOR $vA, $vA)>; -def : Pat<(vnot_ppc (or v4i32:$A, v4i32:$B)), +def : Pat<(vnot (or v4i32:$A, v4i32:$B)), (VNOR $A, $B)>; -def : Pat<(and v4i32:$A, (vnot_ppc v4i32:$B)), +def : Pat<(and v4i32:$A, (vnot v4i32:$B)), (VANDC $A, $B)>; def : Pat<(fmul v4f32:$vA, v4f32:$vB), @@ -1142,17 +1137,17 @@ def : Pat<(v2f64 (vselect v2i64:$vA, v2f64:$vB, v2f64:$vC)), (VSEL $vC, $vB, $vA)>; // Vector Integer Average Instructions -def : Pat<(v4i32 (sra (sub v4i32:$vA, (vnot_ppc v4i32:$vB)), +def : Pat<(v4i32 (sra (sub v4i32:$vA, (vnot v4i32:$vB)), (v4i32 (immEQOneV)))), (v4i32 (VAVGSW $vA, $vB))>; -def : Pat<(v8i16 (sra (sub v8i16:$vA, (v8i16 (bitconvert(vnot_ppc v4i32:$vB)))), +def : Pat<(v8i16 (sra (sub v8i16:$vA, (v8i16 (bitconvert(vnot v4i32:$vB)))), (v8i16 (immEQOneV)))), (v8i16 (VAVGSH $vA, $vB))>; -def : Pat<(v16i8 (sra (sub v16i8:$vA, (v16i8 (bitconvert(vnot_ppc v4i32:$vB)))), +def : Pat<(v16i8 (sra (sub v16i8:$vA, (v16i8 (bitconvert(vnot v4i32:$vB)))), (v16i8 (immEQOneV)))), (v16i8 (VAVGSB $vA, $vB))>; -def : Pat<(v4i32 (srl (sub v4i32:$vA, (vnot_ppc v4i32:$vB)), +def : Pat<(v4i32 (srl (sub v4i32:$vA, (vnot v4i32:$vB)), (v4i32 (immEQOneV)))), (v4i32 (VAVGUW $vA, $vB))>; -def : Pat<(v8i16 (srl (sub v8i16:$vA, (v8i16 (bitconvert(vnot_ppc v4i32:$vB)))), +def : Pat<(v8i16 (srl (sub v8i16:$vA, (v8i16 (bitconvert(vnot v4i32:$vB)))), (v8i16 (immEQOneV)))), (v8i16 (VAVGUH $vA, $vB))>; -def : Pat<(v16i8 (srl (sub v16i8:$vA, (v16i8 (bitconvert(vnot_ppc v4i32:$vB)))), +def : Pat<(v16i8 (srl (sub v16i8:$vA, (v16i8 (bitconvert(vnot v4i32:$vB)))), (v16i8 (immEQOneV)))), (v16i8 (VAVGUB $vA, $vB))>; } // end HasAltivec @@ -1299,16 +1294,16 @@ let isCommutable = 1 in { // if we find situations where Altivec is really preferred over VSX. def VEQV : VXForm_1<1668, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), "veqv $vD, $vA, $vB", IIC_VecGeneral, - [(set v4i32:$vD, (vnot_ppc (xor v4i32:$vA, v4i32:$vB)))]>; + [(set v4i32:$vD, (vnot (xor v4i32:$vA, v4i32:$vB)))]>; def VNAND : VXForm_1<1412, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), "vnand $vD, $vA, $vB", IIC_VecGeneral, - [(set v4i32:$vD, (vnot_ppc (and v4i32:$vA, v4i32:$vB)))]>; + [(set v4i32:$vD, (vnot (and v4i32:$vA, v4i32:$vB)))]>; } // isCommutable def VORC : VXForm_1<1348, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), "vorc $vD, $vA, $vB", IIC_VecGeneral, [(set v4i32:$vD, (or v4i32:$vA, - (vnot_ppc v4i32:$vB)))]>; + (vnot v4i32:$vB)))]>; // i64 element comparisons. def VCMPEQUD : VCMP <199, "vcmpequd $vD, $vA, $vB" , v2i64>; @@ -1503,8 +1498,7 @@ def VNEGW : VX_VT5_EO5_VB5<1538, 6, "vnegw", def VNEGD : VX_VT5_EO5_VB5<1538, 7, "vnegd", [(set v2i64:$vD, - (sub (v2i64 (bitconvert (v4i32 immAllZerosV))), - v2i64:$vB))]>; + (sub (v2i64 immAllZerosV), v2i64:$vB))]>; // Vector Parity Byte def VPRTYBW : VX_VT5_EO5_VB5<1538, 8, "vprtybw", [(set v4i32:$vD, diff --git a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td index b9eb3b3..fa6fb65 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td +++ b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td @@ -2615,33 +2615,30 @@ let AddedComplexity = 400, Predicates = [PrefixInstrs] in { // and(A, or(B, C)) def : xxevalPattern<(and v4i32:$vA, (or v4i32:$vB, v4i32:$vC)), 7>; // and(A, nor(B, C)) - def : xxevalPattern<(and v4i32:$vA, (vnot_ppc (or v4i32:$vB, v4i32:$vC))), - 8>; + def : xxevalPattern<(and v4i32:$vA, (vnot (or v4i32:$vB, v4i32:$vC))), 8>; // and(A, eqv(B, C)) - def : xxevalPattern<(and v4i32:$vA, (vnot_ppc (xor v4i32:$vB, v4i32:$vC))), - 9>; + def : xxevalPattern<(and v4i32:$vA, (vnot (xor v4i32:$vB, v4i32:$vC))), 9>; // and(A, nand(B, C)) - def : xxevalPattern<(and v4i32:$vA, (vnot_ppc (and v4i32:$vB, v4i32:$vC))), - 14>; + def : xxevalPattern<(and v4i32:$vA, (vnot (and v4i32:$vB, v4i32:$vC))), 14>; // NAND // nand(A, B, C) - def : xxevalPattern<(vnot_ppc (and v4i32:$vA, (and v4i32:$vB, v4i32:$vC))), + def : xxevalPattern<(vnot (and v4i32:$vA, (and v4i32:$vB, v4i32:$vC))), !sub(255, 1)>; // nand(A, xor(B, C)) - def : xxevalPattern<(vnot_ppc (and v4i32:$vA, (xor v4i32:$vB, v4i32:$vC))), + def : xxevalPattern<(vnot (and v4i32:$vA, (xor v4i32:$vB, v4i32:$vC))), !sub(255, 6)>; // nand(A, or(B, C)) - def : xxevalPattern<(vnot_ppc (and v4i32:$vA, (or v4i32:$vB, v4i32:$vC))), + def : xxevalPattern<(vnot (and v4i32:$vA, (or v4i32:$vB, v4i32:$vC))), !sub(255, 7)>; // nand(A, nor(B, C)) - def : xxevalPattern<(or (vnot_ppc v4i32:$vA), (or v4i32:$vB, v4i32:$vC)), + def : xxevalPattern<(or (vnot v4i32:$vA), (or v4i32:$vB, v4i32:$vC)), !sub(255, 8)>; // nand(A, eqv(B, C)) - def : xxevalPattern<(or (vnot_ppc v4i32:$vA), (xor v4i32:$vB, v4i32:$vC)), + def : xxevalPattern<(or (vnot v4i32:$vA), (xor v4i32:$vB, v4i32:$vC)), !sub(255, 9)>; // nand(A, nand(B, C)) - def : xxevalPattern<(or (vnot_ppc v4i32:$vA), (and v4i32:$vB, v4i32:$vC)), + def : xxevalPattern<(or (vnot v4i32:$vA), (and v4i32:$vB, v4i32:$vC)), !sub(255, 14)>; } diff --git a/llvm/lib/Target/PowerPC/PPCInstrVSX.td b/llvm/lib/Target/PowerPC/PPCInstrVSX.td index db6e00c..7eace18 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrVSX.td +++ b/llvm/lib/Target/PowerPC/PPCInstrVSX.td @@ -1009,13 +1009,13 @@ let hasSideEffects = 0 in { (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), "xxlandc $XT, $XA, $XB", IIC_VecGeneral, [(set v4i32:$XT, (and v4i32:$XA, - (vnot_ppc v4i32:$XB)))]>; + (vnot v4i32:$XB)))]>; let isCommutable = 1 in { def XXLNOR : XX3Form<60, 162, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), "xxlnor $XT, $XA, $XB", IIC_VecGeneral, - [(set v4i32:$XT, (vnot_ppc (or v4i32:$XA, - v4i32:$XB)))]>; + [(set v4i32:$XT, (vnot (or v4i32:$XA, + v4i32:$XB)))]>; def XXLOR : XX3Form<60, 146, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), "xxlor $XT, $XA, $XB", IIC_VecGeneral, @@ -1092,12 +1092,11 @@ let Predicates = [HasVSX, HasP8Vector] in { def XXLEQV : XX3Form<60, 186, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), "xxleqv $XT, $XA, $XB", IIC_VecGeneral, - [(set v4i32:$XT, (vnot_ppc (xor v4i32:$XA, v4i32:$XB)))]>; + [(set v4i32:$XT, (vnot (xor v4i32:$XA, v4i32:$XB)))]>; def XXLNAND : XX3Form<60, 178, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), "xxlnand $XT, $XA, $XB", IIC_VecGeneral, - [(set v4i32:$XT, (vnot_ppc (and v4i32:$XA, - v4i32:$XB)))]>; + [(set v4i32:$XT, (vnot (and v4i32:$XA, v4i32:$XB)))]>; } // isCommutable let isCodeGenOnly = 1, isMoveImm = 1, isAsCheapAsAMove = 1, @@ -1110,7 +1109,7 @@ let Predicates = [HasVSX, HasP8Vector] in { def XXLORC : XX3Form<60, 170, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), "xxlorc $XT, $XA, $XB", IIC_VecGeneral, - [(set v4i32:$XT, (or v4i32:$XA, (vnot_ppc v4i32:$XB)))]>; + [(set v4i32:$XT, (or v4i32:$XA, (vnot v4i32:$XB)))]>; // VSX scalar loads introduced in ISA 2.07 let mayLoad = 1, mayStore = 0 in { @@ -2453,9 +2452,9 @@ let Predicates = [HasVSX, IsBigEndian, HasP8Altivec] in let AddedComplexity = 400 in { // Valid for any VSX subtarget, regardless of endianness. let Predicates = [HasVSX] in { -def : Pat<(v4i32 (vnot_ppc v4i32:$A)), +def : Pat<(v4i32 (vnot v4i32:$A)), (v4i32 (XXLNOR $A, $A))>; -def : Pat<(v4i32 (or (and (vnot_ppc v4i32:$C), v4i32:$A), +def : Pat<(v4i32 (or (and (vnot v4i32:$C), v4i32:$A), (and v4i32:$B, v4i32:$C))), (v4i32 (XXSEL $A, $B, $C))>; -- 2.7.4