From 93cff7fb82c861b3ad99872444ebd301d35f9cce Mon Sep 17 00:00:00 2001 From: Ahmed Bougacha Date: Mon, 15 Feb 2016 18:07:29 +0000 Subject: [PATCH] [CodeGen] Document and use getConstant's splat-building feature. NFC. Differential Revision: http://reviews.llvm.org/D17229 llvm-svn: 260901 --- llvm/include/llvm/CodeGen/SelectionDAG.h | 21 +++++- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 9 +-- .../lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 5 +- llvm/lib/Target/ARM/ARMISelLowering.cpp | 9 +-- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 25 ++----- llvm/lib/Target/X86/X86ISelLowering.cpp | 84 ++++++---------------- 6 files changed, 55 insertions(+), 98 deletions(-) diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h b/llvm/include/llvm/CodeGen/SelectionDAG.h index 8845bb5..5e4ddcd 100644 --- a/llvm/include/llvm/CodeGen/SelectionDAG.h +++ b/llvm/include/llvm/CodeGen/SelectionDAG.h @@ -427,6 +427,13 @@ public: //===--------------------------------------------------------------------===// // Node creation methods. // + + /// \brief Create a ConstantSDNode wrapping a constant value. + /// If VT is a vector type, the constant is splatted into a BUILD_VECTOR. + /// + /// If only legal types can be produced, this does the necessary + /// transformations (e.g., if the vector element type is illegal). + /// @{ SDValue getConstant(uint64_t Val, SDLoc DL, EVT VT, bool isTarget = false, bool isOpaque = false); SDValue getConstant(const APInt &Val, SDLoc DL, EVT VT, bool isTarget = false, @@ -446,8 +453,16 @@ public: bool isOpaque = false) { return getConstant(Val, DL, VT, true, isOpaque); } - // The forms below that take a double should only be used for simple - // constants that can be exactly represented in VT. No checks are made. + /// @} + + /// \brief Create a ConstantFPSDNode wrapping a constant value. + /// If VT is a vector type, the constant is splatted into a BUILD_VECTOR. + /// + /// If only legal types can be produced, this does the necessary + /// transformations (e.g., if the vector element type is illegal). + /// The forms that take a double should only be used for simple constants + /// that can be exactly represented in VT. No checks are made. + /// @{ SDValue getConstantFP(double Val, SDLoc DL, EVT VT, bool isTarget = false); SDValue getConstantFP(const APFloat& Val, SDLoc DL, EVT VT, bool isTarget = false); @@ -462,6 +477,8 @@ public: SDValue getTargetConstantFP(const ConstantFP &Val, SDLoc DL, EVT VT) { return getConstantFP(Val, DL, VT, true); } + /// @} + SDValue getGlobalAddress(const GlobalValue *GV, SDLoc DL, EVT VT, int64_t offset = 0, bool isTargetGA = false, unsigned char TargetFlags = 0); diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 8b1b6bb..4799221 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -6430,10 +6430,8 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors. // Only do this before legalize for now. - EVT EltVT = VT.getVectorElementType(); SDLoc DL(N); - SmallVector OneOps(VT.getVectorNumElements(), - DAG.getConstant(1, DL, EltVT)); + SDValue VecOnes = DAG.getConstant(1, DL, VT); if (VT.getSizeInBits() == N0VT.getSizeInBits()) // We know that the # elements of the results is the same as the // # elements of the compare (and the # elements of the compare result @@ -6444,8 +6442,7 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { DAG.getSetCC(DL, VT, N0.getOperand(0), N0.getOperand(1), cast(N0.getOperand(2))->get()), - DAG.getNode(ISD::BUILD_VECTOR, DL, VT, - OneOps)); + VecOnes); // If the desired elements are smaller or larger than the source // elements we can use a matching integer vector type and then @@ -6462,7 +6459,7 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { cast(N0.getOperand(2))->get()); return DAG.getNode(ISD::AND, DL, VT, DAG.getSExtOrTrunc(VsetCC, DL, VT), - DAG.getNode(ISD::BUILD_VECTOR, DL, VT, OneOps)); + VecOnes); } // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp index c6ebdb5..e9f24a1 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp @@ -863,10 +863,7 @@ SDValue VectorLegalizer::ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op) { int NumSrcElements = SrcVT.getVectorNumElements(); // Build up a zero vector to blend into this one. - EVT SrcScalarVT = SrcVT.getScalarType(); - SDValue ScalarZero = DAG.getTargetConstant(0, DL, SrcScalarVT); - SmallVector BuildVectorOperands(NumSrcElements, ScalarZero); - SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, DL, SrcVT, BuildVectorOperands); + SDValue Zero = DAG.getTargetConstant(0, DL, SrcVT); // Shuffle the incoming lanes into the correct position, and pull all other // lanes from the zero vector. diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index d4c9d723..3e04b30 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -6580,8 +6580,7 @@ LowerSDIV_v4i8(SDValue X, SDValue Y, SDLoc dl, SelectionDAG &DAG) { // float4 result = as_float4(as_int4(xf*recip) + 0xb000); X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y); X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X); - Y = DAG.getConstant(0xb000, dl, MVT::i32); - Y = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Y, Y, Y, Y); + Y = DAG.getConstant(0xb000, dl, MVT::v4i32); X = DAG.getNode(ISD::ADD, dl, MVT::v4i32, X, Y); X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X); // Convert back to short. @@ -6619,8 +6618,7 @@ LowerSDIV_v4i16(SDValue N0, SDValue N1, SDLoc dl, SelectionDAG &DAG) { // float4 result = as_float4(as_int4(xf*recip) + 0x89); N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2); N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0); - N1 = DAG.getConstant(0x89, dl, MVT::i32); - N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1); + N1 = DAG.getConstant(0x89, dl, MVT::v4i32); N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1); N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0); // Convert back to integer and return. @@ -6731,8 +6729,7 @@ static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG) { // float4 result = as_float4(as_int4(xf*recip) + 2); N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2); N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0); - N1 = DAG.getConstant(2, dl, MVT::i32); - N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1); + N1 = DAG.getConstant(2, dl, MVT::v4i32); N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1); N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0); // Convert back to integer and return. diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index cdac55c..731bae4 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -6335,9 +6335,7 @@ SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op, // This can be done with an fma and the 0.5 constant: (V+1.0)*0.5 = 0.5*V+0.5 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value); - SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::f64); - FPHalfs = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64, FPHalfs, FPHalfs, - FPHalfs, FPHalfs); + SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::v4f64); Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs); @@ -6746,11 +6744,7 @@ static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT, EVT CanonicalVT = VTys[SplatSize-1]; // Build a canonical splat for this value. - SDValue Elt = DAG.getConstant(Val, dl, MVT::i32); - SmallVector Ops; - Ops.assign(CanonicalVT.getVectorNumElements(), Elt); - SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, Ops); - return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res); + return DAG.getBitcast(ReqVT, DAG.getConstant(Val, dl, CanonicalVT)); } /// BuildIntrinsicOp - Return a unary operator intrinsic node with the @@ -6919,9 +6913,7 @@ SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op, DAG.getConstant(Intrinsic::ppc_qpx_qvfcfidu, dl, MVT::i32), LoadedVect); - SDValue FPZeros = DAG.getConstantFP(0.0, dl, MVT::f64); - FPZeros = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64, - FPZeros, FPZeros, FPZeros, FPZeros); + SDValue FPZeros = DAG.getConstantFP(0.0, dl, MVT::v4f64); return DAG.getSetCC(dl, MVT::v4i1, LoadedVect, FPZeros, ISD::SETEQ); } @@ -6949,8 +6941,7 @@ SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op, if (SplatBits == 0) { // Canonicalize all zero vectors to be v4i32. if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) { - SDValue Z = DAG.getConstant(0, dl, MVT::i32); - Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z); + SDValue Z = DAG.getConstant(0, dl, MVT::v4i32); Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z); } return Op; @@ -7594,9 +7585,7 @@ SDValue PPCTargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, // FIXME: We can make this an f32 vector, but the BUILD_VECTOR code needs to // understand how to form the extending load. - SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::f64); - FPHalfs = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64, - FPHalfs, FPHalfs, FPHalfs, FPHalfs); + SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::v4f64); Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs); @@ -7811,9 +7800,7 @@ SDValue PPCTargetLowering::LowerVectorStore(SDValue Op, // FIXME: We can make this an f32 vector, but the BUILD_VECTOR code needs to // understand how to form the extending load. - SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::f64); - FPHalfs = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64, - FPHalfs, FPHalfs, FPHalfs, FPHalfs); + SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::v4f64); Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs); diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 24984a9..03d7c1f 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -5984,17 +5984,11 @@ X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const { "Unexpected type in LowerBUILD_VECTORvXi1!"); SDLoc dl(Op); - if (ISD::isBuildVectorAllZeros(Op.getNode())) { - SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1); - SmallVector Ops(VT.getVectorNumElements(), Cst); - return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops); - } + if (ISD::isBuildVectorAllZeros(Op.getNode())) + return DAG.getTargetConstant(0, dl, VT); - if (ISD::isBuildVectorAllOnes(Op.getNode())) { - SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1); - SmallVector Ops(VT.getVectorNumElements(), Cst); - return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops); - } + if (ISD::isBuildVectorAllOnes(Op.getNode())) + return DAG.getTargetConstant(1, dl, VT); if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) { SDValue Imm = ConvertI1VectorToInteger(Op, DAG); @@ -13345,24 +13339,12 @@ static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG, // -- v >> 16 // Create the splat vector for 0x4b000000. - SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32); - SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow, - CstLow, CstLow, CstLow, CstLow}; - SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, - makeArrayRef(&CstLowArray[0], NumElts)); + SDValue VecCstLow = DAG.getConstant(0x4b000000, DL, VecIntVT); // Create the splat vector for 0x53000000. - SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32); - SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh, - CstHigh, CstHigh, CstHigh, CstHigh}; - SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, - makeArrayRef(&CstHighArray[0], NumElts)); + SDValue VecCstHigh = DAG.getConstant(0x53000000, DL, VecIntVT); // Create the right shift. - SDValue CstShift = DAG.getConstant(16, DL, MVT::i32); - SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift, - CstShift, CstShift, CstShift, CstShift}; - SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, - makeArrayRef(&CstShiftArray[0], NumElts)); + SDValue VecCstShift = DAG.getConstant(16, DL, VecIntVT); SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift); SDValue Low, High; @@ -13384,9 +13366,7 @@ static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG, High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast, VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32)); } else { - SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32); - SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask, - CstMask, CstMask, CstMask); + SDValue VecCstMask = DAG.getConstant(0xffff, DL, VecIntVT); // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000; SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask); Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow); @@ -13396,12 +13376,8 @@ static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG, } // Create the vector constant for -(0x1.0p39f + 0x1.0p23f). - SDValue CstFAdd = DAG.getConstantFP( - APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32); - SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd, - CstFAdd, CstFAdd, CstFAdd, CstFAdd}; - SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT, - makeArrayRef(&CstFAddArray[0], NumElts)); + SDValue VecCstFAdd = DAG.getConstantFP( + APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, VecFloatVT); // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f); SDValue HighBitcast = DAG.getBitcast(VecFloatVT, High); @@ -20097,7 +20073,6 @@ static SDValue LowerHorizontalByteSum(SDValue V, MVT VT, SDLoc DL(V); MVT ByteVecVT = V.getSimpleValueType(); MVT EltVT = VT.getVectorElementType(); - int NumElts = VT.getVectorNumElements(); assert(ByteVecVT.getVectorElementType() == MVT::i8 && "Expected value to have byte element type."); assert(EltVT != MVT::i8 && @@ -20148,12 +20123,11 @@ static SDValue LowerHorizontalByteSum(SDValue V, MVT VT, // i8 elements, shift the i16s left by 8, sum as i8s, and then shift as i16s // right by 8. It is important to shift as i16s as i8 vector shift isn't // directly supported. - SmallVector Shifters(NumElts, DAG.getConstant(8, DL, EltVT)); - SDValue Shifter = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters); - SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, DAG.getBitcast(VT, V), Shifter); + SDValue ShifterV = DAG.getConstant(8, DL, VT); + SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, DAG.getBitcast(VT, V), ShifterV); V = DAG.getNode(ISD::ADD, DL, ByteVecVT, DAG.getBitcast(ByteVecVT, Shl), DAG.getBitcast(ByteVecVT, V)); - return DAG.getNode(ISD::SRL, DL, VT, DAG.getBitcast(VT, V), Shifter); + return DAG.getNode(ISD::SRL, DL, VT, DAG.getBitcast(VT, V), ShifterV); } static SDValue LowerVectorCTPOPInRegLUT(SDValue Op, SDLoc DL, @@ -20189,13 +20163,10 @@ static SDValue LowerVectorCTPOPInRegLUT(SDValue Op, SDLoc DL, for (int i = 0; i < NumByteElts; ++i) LUTVec.push_back(DAG.getConstant(LUT[i % 16], DL, MVT::i8)); SDValue InRegLUT = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, LUTVec); - SmallVector Mask0F(NumByteElts, - DAG.getConstant(0x0F, DL, MVT::i8)); - SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Mask0F); + SDValue M0F = DAG.getConstant(0x0F, DL, ByteVecVT); // High nibbles - SmallVector Four(NumByteElts, DAG.getConstant(4, DL, MVT::i8)); - SDValue FourV = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Four); + SDValue FourV = DAG.getConstant(4, DL, ByteVecVT); SDValue HighNibbles = DAG.getNode(ISD::SRL, DL, ByteVecVT, In, FourV); // Low nibbles @@ -20236,19 +20207,13 @@ static SDValue LowerVectorCTPOPBitmath(SDValue Op, SDLoc DL, auto GetShift = [&](unsigned OpCode, SDValue V, int Shifter) { MVT VT = V.getSimpleValueType(); - SmallVector Shifters( - VT.getVectorNumElements(), - DAG.getConstant(Shifter, DL, VT.getVectorElementType())); - return DAG.getNode(OpCode, DL, VT, V, - DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters)); + SDValue ShifterV = DAG.getConstant(Shifter, DL, VT); + return DAG.getNode(OpCode, DL, VT, V, ShifterV); }; auto GetMask = [&](SDValue V, APInt Mask) { MVT VT = V.getSimpleValueType(); - SmallVector Masks( - VT.getVectorNumElements(), - DAG.getConstant(Mask, DL, VT.getVectorElementType())); - return DAG.getNode(ISD::AND, DL, VT, V, - DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Masks)); + SDValue MaskV = DAG.getConstant(Mask, DL, VT); + return DAG.getNode(ISD::AND, DL, VT, V, MaskV); }; // We don't want to incur the implicit masks required to SRL vNi8 vectors on @@ -20975,9 +20940,8 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N, return; SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64, N->getOperand(0)); - SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl, - MVT::f64); - SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias); + SDValue VBias = + DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl, MVT::v2f64); SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn, DAG.getBitcast(MVT::v2i64, VBias)); Or = DAG.getBitcast(MVT::v2f64, Or); @@ -26772,10 +26736,8 @@ static SDValue detectAVGPattern(SDValue In, EVT VT, SelectionDAG &DAG, Operands[0].getOperand(0).getValueType() == VT) { // The pattern is detected. Subtract one from the constant vector, then // demote it and emit X86ISD::AVG instruction. - SDValue One = DAG.getConstant(1, DL, InScalarVT); - SDValue Ones = DAG.getNode(ISD::BUILD_VECTOR, DL, InVT, - SmallVector(NumElems, One)); - Operands[1] = DAG.getNode(ISD::SUB, DL, InVT, Operands[1], Ones); + SDValue VecOnes = DAG.getConstant(1, DL, InVT); + Operands[1] = DAG.getNode(ISD::SUB, DL, InVT, Operands[1], VecOnes); Operands[1] = DAG.getNode(ISD::TRUNCATE, DL, VT, Operands[1]); return DAG.getNode(X86ISD::AVG, DL, VT, Operands[0].getOperand(0), Operands[1]); -- 2.7.4