From 938d0d6d7b37410282b574e851e8f9bb457a8a1a Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Wed, 7 Dec 2022 09:33:40 -0800 Subject: [PATCH] [RISCV] Replace uses of hasStdExtC with COrZca. Except MakeCompressible which will need more work. Reviewed By: reames Differential Revision: https://reviews.llvm.org/D139504 --- llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp | 3 ++- llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp | 1 + llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 2 +- llvm/test/CodeGen/RISCV/add-before-shl.ll | 4 ++++ 4 files changed, 8 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp index 9b9c23d..8a8e17e 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp @@ -366,7 +366,8 @@ InstSeq generateInstSeq(int64_t Val, const FeatureBitset &ActiveFeatures) { int getIntMatCost(const APInt &Val, unsigned Size, const FeatureBitset &ActiveFeatures, bool CompressionCost) { bool IsRV64 = ActiveFeatures[RISCV::Feature64Bit]; - bool HasRVC = CompressionCost && ActiveFeatures[RISCV::FeatureStdExtC]; + bool HasRVC = CompressionCost && (ActiveFeatures[RISCV::FeatureStdExtC] || + ActiveFeatures[RISCV::FeatureExtZca]); int PlatRegSize = IsRV64 ? 64 : 32; // Split the constant into platform register sized chunks, and calculate cost diff --git a/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp b/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp index dad0aa4..39d0a20 100644 --- a/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp +++ b/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp @@ -332,6 +332,7 @@ bool RISCVMakeCompressibleOpt::runOnMachineFunction(MachineFunction &Fn) { const RISCVInstrInfo &TII = *STI.getInstrInfo(); // This optimization only makes sense if compressed instructions are emitted. + // FIXME: Support Zca, Zcf, Zcd granularity. if (!STI.hasStdExtC()) return false; diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp index 9fbc2db..8c893a5 100644 --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp @@ -562,7 +562,7 @@ void RISCVRegisterInfo::getOffsetOpcodes(const StackOffset &Offset, unsigned RISCVRegisterInfo::getRegisterCostTableIndex(const MachineFunction &MF) const { - return MF.getSubtarget().hasStdExtC() ? 1 : 0; + return MF.getSubtarget().hasStdExtCOrZca() ? 1 : 0; } // Add two address hints to improve chances of being able to use a compressed diff --git a/llvm/test/CodeGen/RISCV/add-before-shl.ll b/llvm/test/CodeGen/RISCV/add-before-shl.ll index dd20dd2..17e028d 100644 --- a/llvm/test/CodeGen/RISCV/add-before-shl.ll +++ b/llvm/test/CodeGen/RISCV/add-before-shl.ll @@ -7,6 +7,10 @@ ; RUN: < %s | FileCheck -check-prefixes=RV32C %s ; RUN: llc -mtriple=riscv64 -mattr=+c -verify-machineinstrs --riscv-no-aliases \ ; RUN: < %s | FileCheck -check-prefixes=RV64C %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zca -verify-machineinstrs --riscv-no-aliases \ +; RUN: < %s | FileCheck -check-prefixes=RV32C %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zca -verify-machineinstrs --riscv-no-aliases \ +; RUN: < %s | FileCheck -check-prefixes=RV64C %s ; These test that constant adds are not moved after shifts by DAGCombine, ; if the constant is cheaper to materialise before it has been shifted. -- 2.7.4