From 9383b098580556ec2db65163e2ba5404fa2d3d94 Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Thu, 21 Jul 2022 11:12:14 +0100 Subject: [PATCH] [AMDGPU][GlobalISel] Fix subtarget checks for combining to v_med3_i16 Differential Revision: https://reviews.llvm.org/D130243 --- llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp | 5 +- llvm/test/CodeGen/AMDGPU/GlobalISel/smed3.ll | 117 +++++++++++++---------- llvm/test/CodeGen/AMDGPU/GlobalISel/umed3.ll | 117 +++++++++++++---------- 3 files changed, 134 insertions(+), 105 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp index 0df6f4d..bd8e568 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp @@ -153,7 +153,10 @@ bool AMDGPURegBankCombinerHelper::matchIntMinMaxToMed3( if (!isVgprRegBank(Dst)) return false; - if (MRI.getType(Dst).isVector()) + // med3 for i16 is only available on gfx9+, and not available for v2i16. + LLT Ty = MRI.getType(Dst); + if ((Ty != LLT::scalar(16) || !Subtarget.hasMed3_16()) && + Ty != LLT::scalar(32)) return false; MinMaxMedOpc OpcodeTriple = getMinMaxPair(MI.getOpcode()); diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/smed3.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/smed3.ll index dca2c01..bb021f3 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/smed3.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/smed3.ll @@ -1,13 +1,14 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 %s +; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx802 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX89,GFX8 %s +; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX89,GFX9 %s ; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s define i32 @test_min_max_ValK0_K1_i32(i32 %a) { -; GFX9-LABEL: test_min_max_ValK0_K1_i32: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_med3_i32 v0, v0, -12, 17 -; GFX9-NEXT: s_setpc_b64 s[30:31] +; GFX89-LABEL: test_min_max_ValK0_K1_i32: +; GFX89: ; %bb.0: +; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX89-NEXT: v_med3_i32 v0, v0, -12, 17 +; GFX89-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: test_min_max_ValK0_K1_i32: ; GFX10: ; %bb.0: @@ -21,11 +22,11 @@ define i32 @test_min_max_ValK0_K1_i32(i32 %a) { } define i32 @min_max_ValK0_K1_i32(i32 %a) { -; GFX9-LABEL: min_max_ValK0_K1_i32: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_med3_i32 v0, v0, -12, 17 -; GFX9-NEXT: s_setpc_b64 s[30:31] +; GFX89-LABEL: min_max_ValK0_K1_i32: +; GFX89: ; %bb.0: +; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX89-NEXT: v_med3_i32 v0, v0, -12, 17 +; GFX89-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: min_max_ValK0_K1_i32: ; GFX10: ; %bb.0: @@ -39,11 +40,11 @@ define i32 @min_max_ValK0_K1_i32(i32 %a) { } define i32 @test_min_K1max_ValK0__i32(i32 %a) { -; GFX9-LABEL: test_min_K1max_ValK0__i32: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_med3_i32 v0, v0, -12, 17 -; GFX9-NEXT: s_setpc_b64 s[30:31] +; GFX89-LABEL: test_min_K1max_ValK0__i32: +; GFX89: ; %bb.0: +; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX89-NEXT: v_med3_i32 v0, v0, -12, 17 +; GFX89-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: test_min_K1max_ValK0__i32: ; GFX10: ; %bb.0: @@ -57,11 +58,11 @@ define i32 @test_min_K1max_ValK0__i32(i32 %a) { } define i32 @test_min_K1max_K0Val__i32(i32 %a) { -; GFX9-LABEL: test_min_K1max_K0Val__i32: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_med3_i32 v0, v0, -12, 17 -; GFX9-NEXT: s_setpc_b64 s[30:31] +; GFX89-LABEL: test_min_K1max_K0Val__i32: +; GFX89: ; %bb.0: +; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX89-NEXT: v_med3_i32 v0, v0, -12, 17 +; GFX89-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: test_min_K1max_K0Val__i32: ; GFX10: ; %bb.0: @@ -75,11 +76,11 @@ define i32 @test_min_K1max_K0Val__i32(i32 %a) { } define i32 @test_max_min_ValK1_K0_i32(i32 %a) { -; GFX9-LABEL: test_max_min_ValK1_K0_i32: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_med3_i32 v0, v0, -12, 17 -; GFX9-NEXT: s_setpc_b64 s[30:31] +; GFX89-LABEL: test_max_min_ValK1_K0_i32: +; GFX89: ; %bb.0: +; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX89-NEXT: v_med3_i32 v0, v0, -12, 17 +; GFX89-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: test_max_min_ValK1_K0_i32: ; GFX10: ; %bb.0: @@ -93,11 +94,11 @@ define i32 @test_max_min_ValK1_K0_i32(i32 %a) { } define i32 @test_max_min_K1Val_K0_i32(i32 %a) { -; GFX9-LABEL: test_max_min_K1Val_K0_i32: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_med3_i32 v0, v0, -12, 17 -; GFX9-NEXT: s_setpc_b64 s[30:31] +; GFX89-LABEL: test_max_min_K1Val_K0_i32: +; GFX89: ; %bb.0: +; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX89-NEXT: v_med3_i32 v0, v0, -12, 17 +; GFX89-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: test_max_min_K1Val_K0_i32: ; GFX10: ; %bb.0: @@ -111,11 +112,11 @@ define i32 @test_max_min_K1Val_K0_i32(i32 %a) { } define i32 @test_max_K0min_ValK1__i32(i32 %a) { -; GFX9-LABEL: test_max_K0min_ValK1__i32: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_med3_i32 v0, v0, -12, 17 -; GFX9-NEXT: s_setpc_b64 s[30:31] +; GFX89-LABEL: test_max_K0min_ValK1__i32: +; GFX89: ; %bb.0: +; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX89-NEXT: v_med3_i32 v0, v0, -12, 17 +; GFX89-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: test_max_K0min_ValK1__i32: ; GFX10: ; %bb.0: @@ -129,11 +130,11 @@ define i32 @test_max_K0min_ValK1__i32(i32 %a) { } define i32 @test_max_K0min_K1Val__i32(i32 %a) { -; GFX9-LABEL: test_max_K0min_K1Val__i32: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_med3_i32 v0, v0, -12, 17 -; GFX9-NEXT: s_setpc_b64 s[30:31] +; GFX89-LABEL: test_max_K0min_K1Val__i32: +; GFX89: ; %bb.0: +; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX89-NEXT: v_med3_i32 v0, v0, -12, 17 +; GFX89-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: test_max_K0min_K1Val__i32: ; GFX10: ; %bb.0: @@ -147,6 +148,18 @@ define i32 @test_max_K0min_K1Val__i32(i32 %a) { } define <2 x i16> @test_max_K0min_K1Val__v2i16(<2 x i16> %a) { +; GFX8-LABEL: test_max_K0min_K1Val__v2i16: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v2, 17 +; GFX8-NEXT: v_min_i16_e32 v1, 17, v0 +; GFX8-NEXT: v_min_i16_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX8-NEXT: v_mov_b32_e32 v2, -12 +; GFX8-NEXT: v_max_i16_e32 v1, -12, v1 +; GFX8-NEXT: v_max_i16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX8-NEXT: v_or_b32_e32 v0, v1, v0 +; GFX8-NEXT: s_setpc_b64 s[30:31] +; ; GFX9-LABEL: test_max_K0min_K1Val__v2i16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -167,11 +180,11 @@ define <2 x i16> @test_max_K0min_K1Val__v2i16(<2 x i16> %a) { } define amdgpu_ps i32 @test_uniform_min_max(i32 inreg %a) { -; GFX9-LABEL: test_uniform_min_max: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_max_i32 s0, s2, -12 -; GFX9-NEXT: s_min_i32 s0, s0, 17 -; GFX9-NEXT: ; return to shader part epilog +; GFX89-LABEL: test_uniform_min_max: +; GFX89: ; %bb.0: +; GFX89-NEXT: s_max_i32 s0, s2, -12 +; GFX89-NEXT: s_min_i32 s0, s0, 17 +; GFX89-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: test_uniform_min_max: ; GFX10: ; %bb.0: @@ -184,12 +197,12 @@ define amdgpu_ps i32 @test_uniform_min_max(i32 inreg %a) { } define i32 @test_non_inline_constant_i32(i32 %a) { -; GFX9-LABEL: test_non_inline_constant_i32: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v1, 0x41 -; GFX9-NEXT: v_med3_i32 v0, v0, -12, v1 -; GFX9-NEXT: s_setpc_b64 s[30:31] +; GFX89-LABEL: test_non_inline_constant_i32: +; GFX89: ; %bb.0: +; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX89-NEXT: v_mov_b32_e32 v1, 0x41 +; GFX89-NEXT: v_med3_i32 v0, v0, -12, v1 +; GFX89-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: test_non_inline_constant_i32: ; GFX10: ; %bb.0: diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/umed3.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/umed3.ll index de87e10..35ef787 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/umed3.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/umed3.ll @@ -1,13 +1,14 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 %s +; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx802 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX89,GFX8 %s +; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX89,GFX9 %s ; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s define i32 @test_min_max_ValK0_K1_u32(i32 %a) { -; GFX9-LABEL: test_min_max_ValK0_K1_u32: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_med3_u32 v0, v0, 12, 17 -; GFX9-NEXT: s_setpc_b64 s[30:31] +; GFX89-LABEL: test_min_max_ValK0_K1_u32: +; GFX89: ; %bb.0: +; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX89-NEXT: v_med3_u32 v0, v0, 12, 17 +; GFX89-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: test_min_max_ValK0_K1_u32: ; GFX10: ; %bb.0: @@ -21,11 +22,11 @@ define i32 @test_min_max_ValK0_K1_u32(i32 %a) { } define i32 @min_max_ValK0_K1_i32(i32 %a) { -; GFX9-LABEL: min_max_ValK0_K1_i32: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_med3_u32 v0, v0, 12, 17 -; GFX9-NEXT: s_setpc_b64 s[30:31] +; GFX89-LABEL: min_max_ValK0_K1_i32: +; GFX89: ; %bb.0: +; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX89-NEXT: v_med3_u32 v0, v0, 12, 17 +; GFX89-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: min_max_ValK0_K1_i32: ; GFX10: ; %bb.0: @@ -39,11 +40,11 @@ define i32 @min_max_ValK0_K1_i32(i32 %a) { } define i32 @test_min_K1max_ValK0__u32(i32 %a) { -; GFX9-LABEL: test_min_K1max_ValK0__u32: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_med3_u32 v0, v0, 12, 17 -; GFX9-NEXT: s_setpc_b64 s[30:31] +; GFX89-LABEL: test_min_K1max_ValK0__u32: +; GFX89: ; %bb.0: +; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX89-NEXT: v_med3_u32 v0, v0, 12, 17 +; GFX89-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: test_min_K1max_ValK0__u32: ; GFX10: ; %bb.0: @@ -57,11 +58,11 @@ define i32 @test_min_K1max_ValK0__u32(i32 %a) { } define i32 @test_min_K1max_K0Val__u32(i32 %a) { -; GFX9-LABEL: test_min_K1max_K0Val__u32: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_med3_u32 v0, v0, 12, 17 -; GFX9-NEXT: s_setpc_b64 s[30:31] +; GFX89-LABEL: test_min_K1max_K0Val__u32: +; GFX89: ; %bb.0: +; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX89-NEXT: v_med3_u32 v0, v0, 12, 17 +; GFX89-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: test_min_K1max_K0Val__u32: ; GFX10: ; %bb.0: @@ -75,11 +76,11 @@ define i32 @test_min_K1max_K0Val__u32(i32 %a) { } define i32 @test_max_min_ValK1_K0_u32(i32 %a) { -; GFX9-LABEL: test_max_min_ValK1_K0_u32: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_med3_u32 v0, v0, 12, 17 -; GFX9-NEXT: s_setpc_b64 s[30:31] +; GFX89-LABEL: test_max_min_ValK1_K0_u32: +; GFX89: ; %bb.0: +; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX89-NEXT: v_med3_u32 v0, v0, 12, 17 +; GFX89-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: test_max_min_ValK1_K0_u32: ; GFX10: ; %bb.0: @@ -93,11 +94,11 @@ define i32 @test_max_min_ValK1_K0_u32(i32 %a) { } define i32 @test_max_min_K1Val_K0_u32(i32 %a) { -; GFX9-LABEL: test_max_min_K1Val_K0_u32: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_med3_u32 v0, v0, 12, 17 -; GFX9-NEXT: s_setpc_b64 s[30:31] +; GFX89-LABEL: test_max_min_K1Val_K0_u32: +; GFX89: ; %bb.0: +; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX89-NEXT: v_med3_u32 v0, v0, 12, 17 +; GFX89-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: test_max_min_K1Val_K0_u32: ; GFX10: ; %bb.0: @@ -111,11 +112,11 @@ define i32 @test_max_min_K1Val_K0_u32(i32 %a) { } define i32 @test_max_K0min_ValK1__u32(i32 %a) { -; GFX9-LABEL: test_max_K0min_ValK1__u32: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_med3_u32 v0, v0, 12, 17 -; GFX9-NEXT: s_setpc_b64 s[30:31] +; GFX89-LABEL: test_max_K0min_ValK1__u32: +; GFX89: ; %bb.0: +; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX89-NEXT: v_med3_u32 v0, v0, 12, 17 +; GFX89-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: test_max_K0min_ValK1__u32: ; GFX10: ; %bb.0: @@ -129,11 +130,11 @@ define i32 @test_max_K0min_ValK1__u32(i32 %a) { } define i32 @test_max_K0min_K1Val__u32(i32 %a) { -; GFX9-LABEL: test_max_K0min_K1Val__u32: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_med3_u32 v0, v0, 12, 17 -; GFX9-NEXT: s_setpc_b64 s[30:31] +; GFX89-LABEL: test_max_K0min_K1Val__u32: +; GFX89: ; %bb.0: +; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX89-NEXT: v_med3_u32 v0, v0, 12, 17 +; GFX89-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: test_max_K0min_K1Val__u32: ; GFX10: ; %bb.0: @@ -147,6 +148,18 @@ define i32 @test_max_K0min_K1Val__u32(i32 %a) { } define <2 x i16> @test_max_K0min_K1Val__v2u16(<2 x i16> %a) { +; GFX8-LABEL: test_max_K0min_K1Val__v2u16: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v2, 17 +; GFX8-NEXT: v_min_u16_e32 v1, 17, v0 +; GFX8-NEXT: v_min_u16_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX8-NEXT: v_mov_b32_e32 v2, 12 +; GFX8-NEXT: v_max_u16_e32 v1, 12, v1 +; GFX8-NEXT: v_max_u16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX8-NEXT: v_or_b32_e32 v0, v1, v0 +; GFX8-NEXT: s_setpc_b64 s[30:31] +; ; GFX9-LABEL: test_max_K0min_K1Val__v2u16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -167,11 +180,11 @@ define <2 x i16> @test_max_K0min_K1Val__v2u16(<2 x i16> %a) { } define amdgpu_ps i32 @test_uniform_min_max(i32 inreg %a) { -; GFX9-LABEL: test_uniform_min_max: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_max_u32 s0, s2, 12 -; GFX9-NEXT: s_min_u32 s0, s0, 17 -; GFX9-NEXT: ; return to shader part epilog +; GFX89-LABEL: test_uniform_min_max: +; GFX89: ; %bb.0: +; GFX89-NEXT: s_max_u32 s0, s2, 12 +; GFX89-NEXT: s_min_u32 s0, s0, 17 +; GFX89-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: test_uniform_min_max: ; GFX10: ; %bb.0: @@ -184,12 +197,12 @@ define amdgpu_ps i32 @test_uniform_min_max(i32 inreg %a) { } define i32 @test_non_inline_constant_u32(i32 %a) { -; GFX9-LABEL: test_non_inline_constant_u32: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v1, 0x41 -; GFX9-NEXT: v_med3_u32 v0, v0, 12, v1 -; GFX9-NEXT: s_setpc_b64 s[30:31] +; GFX89-LABEL: test_non_inline_constant_u32: +; GFX89: ; %bb.0: +; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX89-NEXT: v_mov_b32_e32 v1, 0x41 +; GFX89-NEXT: v_med3_u32 v0, v0, 12, v1 +; GFX89-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: test_non_inline_constant_u32: ; GFX10: ; %bb.0: -- 2.7.4