From 937fe722327e674b973b90e37bc4b03a99597805 Mon Sep 17 00:00:00 2001 From: Fred Fish Date: Sun, 5 Jan 1997 19:29:42 +0000 Subject: [PATCH] * tic80-dis.c (M_SI, M_LI): Add macros to test for ":m" modifier bit in an instruction. * tic80-dis.c (print_insn_tic80): Change comma and paren handling. Use M_SI and M_LI macros to check for ":m" modifier for GPR operands. * tic80-opc.c (tic80_operands): Add REGM_SI and REGM_LI operands. (F, M_REG, M_LI, M_SI, SZ_REG, SZ_LI, SZ_SI, D, S): New bit-twiddlers. (MASK_LI_M, MASK_SI_M, MASK_REG_M): Remove and replace in opcode masks with "MASK_* & ~M_*" to get the M bit reset. (tic80_opcodes): Add bsr, bsr.a, cmnd, cmp, dcachec, and dcachef. --- opcodes/ChangeLog | 12 ++++ opcodes/tic80-dis.c | 47 ++++++++------- opcodes/tic80-opc.c | 161 +++++++++++++++++++++++++++++++++++++--------------- 3 files changed, 155 insertions(+), 65 deletions(-) diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index c0c820a..5e525e1 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,4 +1,16 @@ start-sanitize-tic80 +Sun Jan 5 12:18:14 1997 Fred Fish + + * tic80-dis.c (M_SI, M_LI): Add macros to test for ":m" modifier bit + in an instruction. + * tic80-dis.c (print_insn_tic80): Change comma and paren handling. + Use M_SI and M_LI macros to check for ":m" modifier for GPR operands. + * tic80-opc.c (tic80_operands): Add REGM_SI and REGM_LI operands. + (F, M_REG, M_LI, M_SI, SZ_REG, SZ_LI, SZ_SI, D, S): New bit-twiddlers. + (MASK_LI_M, MASK_SI_M, MASK_REG_M): Remove and replace in opcode + masks with "MASK_* & ~M_*" to get the M bit reset. + (tic80_opcodes): Add bsr, bsr.a, cmnd, cmp, dcachec, and dcachef. + Sat Jan 4 19:05:05 1997 Fred Fish * tic80-dis.c (print_insn_tic80): Print TIC80_OPERAND_RELATIVE diff --git a/opcodes/tic80-dis.c b/opcodes/tic80-dis.c index 2cb0753..c615e9b 100644 --- a/opcodes/tic80-dis.c +++ b/opcodes/tic80-dis.c @@ -21,6 +21,9 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "opcode/tic80.h" #include "dis-asm.h" +#define M_SI(insn,op) ((((op) -> flags & TIC80_OPERAND_M_SI) != 0) && ((insn) & (1 << 17))) +#define M_LI(insn,op) ((((op) -> flags & TIC80_OPERAND_M_LI) != 0) && ((insn) & (1 << 15))) + int print_insn_tic80 (memaddr, info) bfd_vma memaddr; @@ -33,8 +36,7 @@ print_insn_tic80 (memaddr, info) const struct tic80_opcode *opcode_end; const unsigned char *opindex; const struct tic80_operand *operand; - int need_comma; - int need_paren; + int close_paren; int length = 4; status = (*info->read_memory_func) (memaddr, buffer, 4, info); @@ -82,8 +84,6 @@ print_insn_tic80 (memaddr, info) (*info -> fprintf_func) (info -> stream, "%s", opcode -> name); /* Now extract and print the operands. */ - need_comma = 0; - need_paren = 0; if (opcode -> operands[0] != 0) { (*info -> fprintf_func) (info -> stream, "\t"); @@ -127,16 +127,33 @@ print_insn_tic80 (memaddr, info) value -= 1 << operand -> bits; } - if (need_comma) + /* If this operand is enclosed in parenthesis, then print + the open paren, otherwise just print the regular comma + separator, except for the first operand. */ + + if ((operand -> flags & TIC80_OPERAND_PARENS) == 0) { - (*info -> fprintf_func) (info -> stream, ","); - need_comma = 0; + close_paren = 0; + if (opindex != opcode -> operands) + { + (*info -> fprintf_func) (info -> stream, ","); + } + } + else + { + close_paren = 1; + (*info -> fprintf_func) (info -> stream, "("); } /* Print the operand as directed by the flags. */ + if ((operand -> flags & TIC80_OPERAND_GPR) != 0) { (*info -> fprintf_func) (info -> stream, "r%ld", value); + if (M_SI (insn[0], operand) || M_LI (insn[0], operand)) + { + (*info -> fprintf_func) (info -> stream, ":m"); + } } else if ((operand -> flags & TIC80_OPERAND_FPA) != 0) { @@ -275,20 +292,12 @@ print_insn_tic80 (memaddr, info) } } - if (need_paren) - { - (*info -> fprintf_func) (info -> stream, ")"); - need_paren = 0; - } + /* If we printed an open paren before printing this operand, close + it now. The flag gets reset on each loop. */ - if ((operand -> flags & TIC80_OPERAND_PARENS) == 0) + if (close_paren) { - need_comma = 1; - } - else - { - (*info -> fprintf_func) (info -> stream, "("); - need_paren = 1; + (*info -> fprintf_func) (info -> stream, ")"); } } } diff --git a/opcodes/tic80-opc.c b/opcodes/tic80-opc.c index 27b853d..1a5b8bd 100644 --- a/opcodes/tic80-opc.c +++ b/opcodes/tic80-opc.c @@ -122,6 +122,18 @@ const struct tic80_operand tic80_operands[] = #define LICR (SICR + 1) { 32, 0, NULL, NULL, TIC80_OPERAND_CR }, + /* Register in bits 26-22, enclosed in parens and with optional + ":m" flag in bit 17 */ + +#define REGM_SI (LICR + 1) + { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS | TIC80_OPERAND_M_SI }, + + /* Register in bits 26-22, enclosed in parens and with optional + ":m" flag in bit 15 */ + +#define REGM_LI (REGM_SI + 1) + { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS | TIC80_OPERAND_M_LI }, + }; const int tic80_num_operands = sizeof (tic80_operands)/sizeof(*tic80_operands); @@ -131,25 +143,48 @@ const int tic80_num_operands = sizeof (tic80_operands)/sizeof(*tic80_operands); #define FIXME 0 -/* Short-Immediate Format Instructions */ +/* Short-Immediate Format Instructions - basic opcode */ #define OP_SI(x) (((x) & 0x7F) << 15) #define MASK_SI OP_SI(0x7F) -#define MASK_SI_M OP_SI(0x7B) /* Short-Immediate with embedded M bit */ -/* Long-Immediate Format Instructions */ +/* Long-Immediate Format Instructions - basic opcode */ #define OP_LI(x) (((x) & 0x3FF) << 12) #define MASK_LI OP_LI(0x3FF) -#define MASK_LI_M OP_LI(0x3F7) /* Long-Immediate with embedded M bit */ -/* Register Format Instructions */ +/* Register Format Instructions - basic opcode */ #define OP_REG(x) OP_LI(x) /* For readability */ #define MASK_REG MASK_LI /* For readability */ -#define MASK_REG_M MASK_LI_M /* For readability */ +/* The 'F' bit at bit 27 */ +#define F(x) ((x) << 27) + +/* The 'M' bit at bit 15 in register and long immediate opcodes */ +#define M_REG(x) ((x) << 15) +#define M_LI(x) ((x) << 15) + +/* The 'M' bit at bit 17 in short immediate opcodes */ +#define M_SI(x) ((x) << 17) + +/* The 'SZ' field at bits 14-13 in register and long immediate opcodes */ +#define SZ_REG(x) ((x) << 13) +#define SZ_LI(x) ((x) << 13) + +/* The 'SZ' field at bits 16-15 in short immediate opcodes */ +#define SZ_SI(x) ((x) << 15) + +/* The 'D' (direct external memory access) bit at bit 10 in long immediate + and register opcodes. */ +#define D(x) ((x) << 10) + +/* The 'S' (scale offset by data size) bit at bit 11 in long immediate + and register opcodes. */ +#define S(x) ((x) << 11) + + const struct tic80_opcode tic80_opcodes[] = { /* The "nop" instruction is really "rdcr 0,r0". We put it first so that this - specific bit pattern will get dissembled as a nop rather than an rdcr. The + specific bit pattern will get disassembled as a nop rather than an rdcr. The mask of all ones ensures that this will happen. */ {"nop", OP_SI(0x4), ~0, 0, {0} }, @@ -247,36 +282,70 @@ const struct tic80_opcode tic80_opcodes[] = { {"brcr", OP_LI(0x30D), MASK_LI, FMT_LI, {LICR} }, {"brcr", OP_REG(0x30C), MASK_REG, FMT_REG, {REG0} }, + /* Branch and save return - nonannulled */ + + {"bsr", OP_SI(0x40), MASK_SI, FMT_SI, {SSOFF,REG27} }, + {"bsr", OP_LI(0x381), MASK_LI, FMT_LI, {LSOFF,REG27} }, + {"bsr", OP_REG(0x380), MASK_REG, FMT_REG, {REG0,REG27} }, + + /* Branch and save return - annulled */ + + {"bsr.a", OP_SI(0x41), MASK_SI, FMT_SI, {SSOFF,REG27} }, + {"bsr.a", OP_LI(0x383), MASK_LI, FMT_LI, {LSOFF,REG27} }, + {"bsr.a", OP_REG(0x382), MASK_REG, FMT_REG, {REG0,REG27} }, + + /* Send command */ + + {"cmnd", OP_SI(0x2), MASK_SI, FMT_SI, {SUI} }, + {"cmnd", OP_LI(0x305), MASK_LI, FMT_LI, {LUI} }, + {"cmnd", OP_REG(0x304), MASK_REG, FMT_REG, {REG0} }, + + /* Integer compare */ + + {"cmp", OP_SI(0x50), MASK_SI, FMT_SI, {SSI,REG22,REG27} }, + {"cmp", OP_LI(0x3A1), MASK_LI, FMT_LI, {LSI,REG22,REG27} }, + {"cmp", OP_REG(0x3A0), MASK_REG, FMT_REG, {REG0,REG22,REG27} }, + + /* Flush data cache subblock - don't clear subblock preset flag */ + + {"dcachec", OP_SI(0x38), F(1) | (MASK_SI & ~M_SI(1)), FMT_SI, {SSI,REGM_SI} }, + {"dcachec", OP_LI(0x371), F(1) | (MASK_LI & ~M_LI(1)) | S(1) | D(1), FMT_LI, {LSI,REGM_LI} }, + {"dcachec", OP_REG(0x370), F(1) | (MASK_REG & ~M_REG(1)) | S(1) | D(1), FMT_REG, {REG0,REGM_LI} }, + + /* Flush data cache subblock - clear subblock preset flag */ + + {"dcachef", OP_SI(0x38) | F(1), F(1) | (MASK_SI & ~M_SI(1)), FMT_SI, {SSI,REGM_SI} }, + {"dcachef", OP_LI(0x371) | F(1), F(1) | (MASK_LI & ~M_LI(1)) | S(1) | D(1), FMT_LI, {LSI,REGM_LI} }, + {"dcachef", OP_REG(0x370) | F(1), F(1) | (MASK_REG & ~M_REG(1)) | S(1) | D(1), FMT_REG, {REG0,REGM_LI} }, + /* WORK IN PROGRESS BELOW THIS POINT */ - {"cmnd", OP_LI(0x305), MASK_LI, FMT_LI, FIXME}, - {"cmnd", OP_REG(0x304), MASK_REG, FMT_REG, FIXME}, - {"cmnd", OP_SI(0x2), MASK_SI, FMT_SI, FIXME}, {"illop0", OP_SI(0), MASK_SI, FMT_SI, FIXME}, - {"ld", OP_LI(0x345), MASK_LI_M, FMT_LI, FIXME}, - {"ld", OP_REG(0x344), MASK_REG_M, FMT_REG, FIXME}, - {"ld", OP_SI(0x22), MASK_SI_M, FMT_SI, FIXME}, - {"ld.b", OP_LI(0x341), MASK_LI_M, FMT_LI, FIXME}, - {"ld.b", OP_REG(0x340), MASK_REG_M, FMT_REG, FIXME}, - {"ld.b", OP_SI(0x20), MASK_SI_M, FMT_SI, FIXME}, - {"ld.d", OP_LI(0x347), MASK_LI_M, FMT_LI, FIXME}, - {"ld.d", OP_REG(0x346), MASK_REG_M, FMT_REG, FIXME}, - {"ld.d", OP_SI(0x23), MASK_SI_M, FMT_SI, FIXME}, - {"ld.h", OP_LI(0x343), MASK_LI_M, FMT_LI, FIXME}, - {"ld.h", OP_REG(0x342), MASK_REG_M, FMT_REG, FIXME}, - {"ld.h", OP_SI(0x21), MASK_SI_M, FMT_SI, FIXME}, - {"ld.u", OP_LI(0x355), MASK_LI_M, FMT_LI, FIXME}, - {"ld.u", OP_REG(0x354), MASK_REG_M, FMT_REG, FIXME}, - {"ld.u", OP_SI(0x2A), MASK_SI_M, FMT_SI, FIXME}, - {"ld.ub", OP_LI(0x351), MASK_LI_M, FMT_LI, FIXME}, - {"ld.ub", OP_REG(0x350), MASK_REG_M, FMT_REG, FIXME}, - {"ld.ub", OP_SI(0x28), MASK_SI_M, FMT_SI, FIXME}, - {"ld.ud", OP_LI(0x357), MASK_LI_M, FMT_LI, FIXME}, - {"ld.ud", OP_REG(0x356), MASK_REG_M, FMT_REG, FIXME}, - {"ld.ud", OP_SI(0x2B), MASK_SI_M, FMT_SI, FIXME}, - {"ld.uh", OP_LI(0x353), MASK_LI_M, FMT_LI, FIXME}, - {"ld.uh", OP_REG(0x352), MASK_REG_M, FMT_REG, FIXME}, - {"ld.uh", OP_SI(0x29), MASK_SI_M, FMT_SI, FIXME}, + + {"ld", OP_LI(0x345), MASK_LI & ~M_LI(1), FMT_LI, FIXME}, + {"ld", OP_REG(0x344), MASK_REG & ~M_REG(1), FMT_REG, FIXME}, + {"ld", OP_SI(0x22), MASK_SI & ~M_SI(1), FMT_SI, FIXME}, + {"ld.b", OP_LI(0x341), MASK_LI & ~M_LI(1), FMT_LI, FIXME}, + {"ld.b", OP_REG(0x340), MASK_REG & ~M_REG(1), FMT_REG, FIXME}, + {"ld.b", OP_SI(0x20), MASK_SI & ~M_SI(1), FMT_SI, FIXME}, + {"ld.d", OP_LI(0x347), MASK_LI & ~M_LI(1), FMT_LI, FIXME}, + {"ld.d", OP_REG(0x346), MASK_REG & ~M_REG(1), FMT_REG, FIXME}, + {"ld.d", OP_SI(0x23), MASK_SI & ~M_SI(1), FMT_SI, FIXME}, + {"ld.h", OP_LI(0x343), MASK_LI & ~M_LI(1), FMT_LI, FIXME}, + {"ld.h", OP_REG(0x342), MASK_REG & ~M_REG(1), FMT_REG, FIXME}, + {"ld.h", OP_SI(0x21), MASK_SI & ~M_SI(1), FMT_SI, FIXME}, + {"ld.u", OP_LI(0x355), MASK_LI & ~M_LI(1), FMT_LI, FIXME}, + {"ld.u", OP_REG(0x354), MASK_REG & ~M_REG(1), FMT_REG, FIXME}, + {"ld.u", OP_SI(0x2A), MASK_SI & ~M_SI(1), FMT_SI, FIXME}, + {"ld.ub", OP_LI(0x351), MASK_LI & ~M_LI(1), FMT_LI, FIXME}, + {"ld.ub", OP_REG(0x350), MASK_REG & ~M_REG(1), FMT_REG, FIXME}, + {"ld.ub", OP_SI(0x28), MASK_SI & ~M_SI(1), FMT_SI, FIXME}, + {"ld.ud", OP_LI(0x357), MASK_LI & ~M_LI(1), FMT_LI, FIXME}, + {"ld.ud", OP_REG(0x356), MASK_REG & ~M_REG(1), FMT_REG, FIXME}, + {"ld.ud", OP_SI(0x2B), MASK_SI & ~M_SI(1), FMT_SI, FIXME}, + {"ld.uh", OP_LI(0x353), MASK_LI & ~M_LI(1), FMT_LI, FIXME}, + {"ld.uh", OP_REG(0x352), MASK_REG & ~M_REG(1), FMT_REG, FIXME}, + {"ld.uh", OP_SI(0x29), MASK_SI & ~M_SI(1), FMT_SI, FIXME}, {"or.ff", OP_LI(0x33D), MASK_LI, FMT_LI, FIXME}, {"or.ff", OP_REG(0x33C), MASK_REG, FMT_REG, FIXME}, {"or.ff", OP_SI(0x1E), MASK_SI, FMT_SI, FIXME}, @@ -308,18 +377,18 @@ const struct tic80_opcode tic80_opcodes[] = { {"shift.im", OP_SI(0xF), MASK_SI, FMT_SI, FIXME}, {"shift.iz", OP_REG(0x31C), MASK_REG, FMT_REG, FIXME}, {"shift.iz", OP_SI(0xE), MASK_SI, FMT_SI, FIXME}, - {"st", OP_LI(0x365), MASK_LI_M, FMT_LI, FIXME}, - {"st", OP_REG(0x364), MASK_REG_M, FMT_REG, FIXME}, - {"st", OP_SI(0x32), MASK_SI_M, FMT_SI, FIXME}, - {"st.b", OP_LI(0x361), MASK_LI_M, FMT_LI, FIXME}, - {"st.b", OP_REG(0x360), MASK_REG_M, FMT_REG, FIXME}, - {"st.b", OP_SI(0x30), MASK_SI_M, FMT_SI, FIXME}, - {"st.d", OP_LI(0x367), MASK_LI_M, FMT_LI, FIXME}, - {"st.d", OP_REG(0x366), MASK_REG_M, FMT_REG, FIXME}, - {"st.d", OP_SI(0x33), MASK_SI_M, FMT_SI, FIXME}, - {"st.h", OP_LI(0x363), MASK_LI_M, FMT_LI, FIXME}, - {"st.h", OP_REG(0x362), MASK_REG_M, FMT_REG, FIXME}, - {"st.h", OP_SI(0x31), MASK_SI_M, FMT_SI, FIXME}, + {"st", OP_LI(0x365), MASK_LI & ~M_LI(1), FMT_LI, FIXME}, + {"st", OP_REG(0x364), MASK_REG & ~M_REG(1), FMT_REG, FIXME}, + {"st", OP_SI(0x32), MASK_SI & ~M_SI(1), FMT_SI, FIXME}, + {"st.b", OP_LI(0x361), MASK_LI & ~M_LI(1), FMT_LI, FIXME}, + {"st.b", OP_REG(0x360), MASK_REG & ~M_REG(1), FMT_REG, FIXME}, + {"st.b", OP_SI(0x30), MASK_SI & ~M_SI(1), FMT_SI, FIXME}, + {"st.d", OP_LI(0x367), MASK_LI & ~M_LI(1), FMT_LI, FIXME}, + {"st.d", OP_REG(0x366), MASK_REG & ~M_REG(1), FMT_REG, FIXME}, + {"st.d", OP_SI(0x33), MASK_SI & ~M_SI(1), FMT_SI, FIXME}, + {"st.h", OP_LI(0x363), MASK_LI & ~M_LI(1), FMT_LI, FIXME}, + {"st.h", OP_REG(0x362), MASK_REG & ~M_REG(1), FMT_REG, FIXME}, + {"st.h", OP_SI(0x31), MASK_SI & ~M_SI(1), FMT_SI, FIXME}, {"swcr", OP_LI(0x30B), MASK_LI, FMT_LI, FIXME}, {"swcr", OP_REG(0x30A), MASK_REG, FMT_REG, FIXME}, {"swcr", OP_SI(0x5), MASK_SI, FMT_SI, FIXME}, -- 2.7.4