From 936947349aee60900c3c4eaf4cfa5deb377d37a2 Mon Sep 17 00:00:00 2001 From: Farhana Aleen Date: Tue, 3 Apr 2018 21:51:45 +0000 Subject: [PATCH] Revert "MSG" This reverts commit 9a0ce889d1c39c74d69ecad5ce9c875155ae55de. This was committed by mistake. llvm-svn: 329119 --- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 2 +- llvm/test/CodeGen/AMDGPU/fmax3.ll | 12 ------------ llvm/test/CodeGen/AMDGPU/fmin3.ll | 12 ------------ 3 files changed, 1 insertion(+), 25 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 2a7549e..f0d5e92 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -6446,7 +6446,7 @@ SDValue SITargetLowering::performMinMaxCombine(SDNode *N, if (Opc != AMDGPUISD::FMIN_LEGACY && Opc != AMDGPUISD::FMAX_LEGACY && - !VT.isVector() && VT != MVT::f64 && + VT != MVT::f64 && ((VT != MVT::f16 && VT != MVT::i16) || Subtarget->hasMin3Max3_16())) { // max(max(a, b), c) -> max3(a, b, c) // min(min(a, b), c) -> min3(a, b, c) diff --git a/llvm/test/CodeGen/AMDGPU/fmax3.ll b/llvm/test/CodeGen/AMDGPU/fmax3.ll index 6f2007b..2e6d3f3 100644 --- a/llvm/test/CodeGen/AMDGPU/fmax3.ll +++ b/llvm/test/CodeGen/AMDGPU/fmax3.ll @@ -84,21 +84,9 @@ define amdgpu_kernel void @test_fmax3_olt_1_f16(half addrspace(1)* %out, half ad ret void } -; Checks whether the test passes; performMinMaxCombine() should not optimize vector patterns of max3 -; since there are no pack instructions for fmax3. -; GCN-LABEL: {{^}}no_fmax3_v2f16: -define <2 x half> @no_fmax3_v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c, <2 x half> %d) { -entry: - %max = tail call fast <2 x half> @llvm.maxnum.v2f16(<2 x half> %a, <2 x half> %b) - %max1 = tail call fast <2 x half> @llvm.maxnum.v2f16(<2 x half> %c, <2 x half> %max) - %res = tail call fast <2 x half> @llvm.maxnum.v2f16(<2 x half> %max1, <2 x half> %d) - ret <2 x half> %res -} - declare i32 @llvm.amdgcn.workitem.id.x() #1 declare float @llvm.maxnum.f32(float, float) #1 declare half @llvm.maxnum.f16(half, half) #1 -declare <2 x half> @llvm.maxnum.v2f16(<2 x half>, <2 x half>) attributes #0 = { nounwind } attributes #1 = { nounwind readnone speculatable } diff --git a/llvm/test/CodeGen/AMDGPU/fmin3.ll b/llvm/test/CodeGen/AMDGPU/fmin3.ll index af0485d..5fc5895 100644 --- a/llvm/test/CodeGen/AMDGPU/fmin3.ll +++ b/llvm/test/CodeGen/AMDGPU/fmin3.ll @@ -82,21 +82,9 @@ define amdgpu_kernel void @test_fmin3_olt_1_f16(half addrspace(1)* %out, half ad ret void } -; Checks whether the test passes; performMinMaxCombine() should not optimize vector patterns of min3 -; since there are no pack instructions for fmin3. -; GCN-LABEL: {{^}}no_fmin3_v2f16: -define <2 x half> @no_fmin3_v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c, <2 x half> %d) { -entry: - %min = tail call fast <2 x half> @llvm.minnum.v2f16(<2 x half> %a, <2 x half> %b) - %min1 = tail call fast <2 x half> @llvm.minnum.v2f16(<2 x half> %c, <2 x half> %min) - %res = tail call fast <2 x half> @llvm.minnum.v2f16(<2 x half> %min1, <2 x half> %d) - ret <2 x half> %res -} - declare i32 @llvm.amdgcn.workitem.id.x() #1 declare float @llvm.minnum.f32(float, float) #1 declare half @llvm.minnum.f16(half, half) #1 -declare <2 x half> @llvm.minnum.v2f16(<2 x half>, <2 x half>) attributes #0 = { nounwind } attributes #1 = { nounwind readnone speculatable } -- 2.7.4