From 9350900fcd2096d370a7654eef37c3363a38ba3a Mon Sep 17 00:00:00 2001 From: Connor Abbott Date: Thu, 20 May 2021 18:30:12 +0200 Subject: [PATCH] ir3: Only use per-wave pvtmem layout for compute The blob seems to do this since a630, and it fixes spec@glsl-1.30@execution@fs-large-local-array on a650. Part-of: --- src/freedreno/ir3/ir3_shader.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/src/freedreno/ir3/ir3_shader.c b/src/freedreno/ir3/ir3_shader.c index a4bfd88..5f9d679 100644 --- a/src/freedreno/ir3/ir3_shader.c +++ b/src/freedreno/ir3/ir3_shader.c @@ -176,10 +176,13 @@ void * ir3_shader_assemble(struct ir3_shader_variant *v) if (compiler->gpu_id >= 400) v->constlen = align(v->constlen, 4); - /* Use the per-wave layout by default on a6xx. It should result in better - * performance when loads/stores are to a uniform index. + /* Use the per-wave layout by default on a6xx for compute shaders. It + * should result in better performance when loads/stores are to a uniform + * index. */ - v->pvtmem_per_wave = compiler->gpu_id >= 600 && !info->multi_dword_ldp_stp; + v->pvtmem_per_wave = + compiler->gpu_id >= 600 && !info->multi_dword_ldp_stp && + v->type == MESA_SHADER_COMPUTE; fixup_regfootprint(v); -- 2.7.4